公开(公告)号：US20180120924A1

公开(公告)日：2018-05-03

申请号：US15668762

申请日：2017-08-04

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Yoni Aizik ,  Doron Rajwan ,  Nir Rosenzweig ,  Efraim Rotem ,  Barnes Cooper ,  Paul S. Diefenbaugh ,  Guy M. Therien ,  Michael Mishaeli ,  Nadav Shulman ,  Ido Melamed ,  Niv Tokman ,  Alexander Gendler ,  Arik Gihon ,  Yevgeni Sabin ,  Hisham Abu Salah ,  Esfir Natanzon

IPC: G06F1/32 ,  G06F11/07

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F11/0757 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

公开(公告)号：US09766675B2

公开(公告)日：2017-09-19

申请号：US14960264

申请日：2015-12-04

Applicant: Intel Corporation

Inventor： Alexander B. Uan-zo-li ,  Vidoot Ponnala Rathnakar ,  Barnes Cooper

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/266 ,  G06F1/26 ,  G06F1/28 ,  G06F1/3203 ,  G06F1/3206

Abstract: A load associated with one or more components coupled via one or more ports to a first power supply rail is monitored. The one or more components are switched to a second power supply rail, if the load is greater than a predetermined load.

公开(公告)号：US09442558B2

公开(公告)日：2016-09-13

申请号：US14129950

申请日：2013-06-28

Applicant: INTEL CORPORATION

Inventor： Paul S. Diefenbaugh ,  Eugene Gorbatov ,  Andrew Henroid ,  Eric C. Samson ,  Barnes Cooper

IPC: G06F1/32 ,  G06F9/48

CPC classification number: G06F1/3234 ,  G06F1/3246 ,  G06F1/3287 ,  G06F9/4893 ,  Y02D10/24 ,  Y02D50/20

Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.

Abstract translation: 在一个实施例中，一种装置包括多个处理器组件; 通信地耦合到多个处理器组件的一个或多个处理器组件的一个或多个设备组件; 以及控制器，其包括其硬件中的至少一部分的逻辑，用于调度一个或多个强制空闲周期的逻辑，所述强制空闲周期与一个或多个活动周期分布，跨越持续时间的强制空闲周期，在该持续时间期间多个处理器组件和一个 或更多的设备组件同时处于分别在强制空闲时段的隔离子时段期间限定强制空闲功率状态的空闲状态。 公开和要求保护其他实施例。

公开(公告)号：US09354679B2

公开(公告)日：2016-05-31

申请号：US13730386

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Robert Gough ,  Barnes Cooper ,  Basavaraj Astekar ,  Mazen Gedeon ,  Soethiha Soe

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F1/3243 ,  Y02D10/152 ,  Y02D10/16

Abstract: Particular embodiments described herein can offer a method that includes receiving a signal indicating whether at least one device is in a low power mode, determining that the at least one device is in a first thermally benign state based, at least in part, on the signal, and performing a first operation associated with a reduced thermal remediation power consumption.

Abstract translation: 本文描述的特定实施例可以提供一种方法，其包括接收指示至少一个设备是否处于低功率模式的信号，至少部分地基于所述信号确定所述至少一个设备处于第一热良性状态 ，以及执行与降低的热修复功率消耗相关联的第一操作。

公开(公告)号：US09213393B2

公开(公告)日：2015-12-15

申请号：US14258921

申请日：2014-04-22

Applicant: Intel Corporation

Inventor： Barnes Cooper ,  Jaya L. Jeyaseelan ,  Robert E. Gough

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3253 ,  G06F1/3287 ,  Y02D10/151 ,  Y02D50/20

Abstract: A method and apparatus for intelligent power management for low power link states. Some embodiments include methods, apparatuses, and systems for a device coupled to a controller via a link; a link power management engine to alter a power state of the link based on a transaction and some knowledge of future transactions between the device and the controller; and a memory or logic to store the link power management engine. In some embodiments, the memory stores information about at least one of the following: the power state of the link, the device buffering, the controller or device state or a history of transactions. In some embodiments, the device is a peripheral of a computer system. In some embodiments, the method may include transitioning the device to various link states. Other embodiments are described.

Abstract translation: 一种用于低功率链路状态智能电源管理的方法和装置。 一些实施例包括用于经由链路耦合到控制器的设备的方法，设备和系统; 链路功率管理引擎，用于基于事务改变链路的功率状态以及对设备和控制器之间的未来事务的一些知识; 以及用于存储链路电源管理引擎的存储器或逻辑。 在一些实施例中，存储器存储关于以下至少一个的信息：链路的功率状态，设备缓冲，控制器或设备状态或事务历史。 在一些实施例中，设备是计算机系统的外设。 在一些实施例中，该方法可以包括将设备转换到各种链路状态。 描述其他实施例。

公开(公告)号：US09195292B2

公开(公告)日：2015-11-24

申请号：US13927746

申请日：2013-06-26

Applicant: Intel Corporation

Inventor： Barnes Cooper ,  Jeffrey R Wilcox ,  Michael N Derr ,  Neil W Songer ,  Craig S Forbell

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3234 ,  G06F1/3243 ,  Y02D10/152

Abstract: In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event during a reduced power state in the processor, set an exit timer based on a platform latency tolerance, block a first plurality of break events from interrupting the reduced power state, and in response to a expiration of the exit timer, terminate the reduced power state. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核心和电源管理逻辑。 功率管理逻辑可以是响应于处理器中的降低功率状态期间的第一中断事件而设置基于平台等待时间容限的退出定时器，阻止第一多个中断事件中断降低的功率状态，以及 响应于退出定时器的到期，终止降低的功率状态。 描述和要求保护其他实施例。