公开(公告)号：US11355438B2

公开(公告)日：2022-06-07

申请号：US16024707

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Rahul Manepalli ,  Gang Duan

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.

公开(公告)号：US11348718B2

公开(公告)日：2022-05-31

申请号：US16022894

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Kristof Darmawikarta ,  Gang Duan ,  Yonggang Li ,  Sameer Paital

IPC: H01F27/26 ,  H01F27/42 ,  H01L21/768 ,  H01L23/64 ,  H01F27/25 ,  H01F27/245

Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.

公开(公告)号：US20210391264A1

公开(公告)日：2021-12-16

申请号：US16902959

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bai Nie ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Haobo Chen ,  Gang Duan ,  Jason M. Gamba ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Tarek A. Ibrahim ,  Rahul N. Manepalli ,  Deepak Vasant Kulkarni ,  Ravindra Vijay Tanikella

IPC: H01L23/538 ,  H01L21/48

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US11062933B2

公开(公告)日：2021-07-13

申请号：US16037459

申请日：2018-07-17

Applicant: Intel Corporation

Inventor： Jesse C. Jones ,  Gang Duan ,  Yosuke Kanaoka ,  Rahul N. Manepalli

IPC: H01L23/00 ,  H01L21/683 ,  B25B11/00

Abstract: A die placement and coupling apparatus may include a die bonding attachment. The die placement and coupling apparatus may include a compliant head unit that may be adapted to optionally couple with a semiconductor die. The compliant head unit may include a die attach surface that may include a layer of compliant material. The layer of compliant material may be coupled to the compliant head unit. The die attach surface may be adapted to mate with the semiconductor die when the semiconductor die is coupled with the compliant head unit. The layer of compliant material may be adapted to yield in response to an applied force. The die placement and coupling apparatus may include a vacuum port in communication with the die attach surface. The port may be adapted to have a vacuum applied to the port, and the vacuum temporarily holds the semiconductor die to the die attach surface.

公开(公告)号：US20250149455A1

公开(公告)日：2025-05-08

申请号：US18503459

申请日：2023-11-07

Applicant: Intel Corporation

Inventor： Nicholas Haehn ,  Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Gang Duan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface; a material on the surface of the glass layer, the material including a polyimide or a dielectric material; a via including a conductive material, wherein the via extends through the glass layer and through the material on the surface of the glass layer, and wherein the via has a first diameter through the material on the surface, a second diameter at the surface of the glass layer, and the first diameter is equal to the second diameter plus 1 micron or minus 1 micron; and a dielectric layer on the material at the surface of the glass layer, the dielectric layer including a conductive pathway electrically coupled to the via.

公开(公告)号：US20250112163A1

公开(公告)日：2025-04-03

申请号：US18375203

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Pratyush Mishra ,  Pratyasha Mohapatra ,  Srinivas Pietambaram ,  Whitney Bryks ,  Mahdi Mohammadighaleni ,  Joshua Stacey ,  Travis Palmer ,  Yosef Kornbluth ,  Kuang Liu ,  Astitva Tripathi ,  Yuqin Li ,  Rengarajan Shanmugam ,  Xing Sun ,  Brian Balch ,  Darko Grujicic ,  Jieying Kong ,  Nicholas Haehn ,  Jacob Vehonsky ,  Mitchell Page ,  Vincent Obiozo Eze ,  Daniel Wandera ,  Sameer Paital ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/15 ,  H01L25/065

Abstract: An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged nanoparticles.

公开(公告)号：US20250110289A1

公开(公告)日：2025-04-03

申请号：US18479004

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Benjamin T. Duong ,  Gang Duan ,  Sandeep Gaan ,  Donald Hammon ,  Wesley B. Morgan

IPC: G02B6/38

Abstract: A ferrule of an optical connector device is to accept one or more optical fibers in one or more fiber holes of the ferrule, the ferrule is formed from a dielectric material. The ferrule includes a face to interface with an optical socket of another device, where ends of the one or more optical fibers are exposed at the face to communicate photon signals with another device. The ferrule further includes alignment features formed in the dielectric layer to align the ends of the one or more optical fibers with one or more waveguides of the other device.

公开(公告)号：US20250105156A1

公开(公告)日：2025-03-27

申请号：US18473479

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Srinivas V. Pietambaram ,  Bohan Shan ,  Gang Duan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L25/065

Abstract: Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a surface, the glass layer including conductive through-glass vias (TGVs); a dielectric layer at the surface of the glass layer, the dielectric layer including conductive pathways; and interconnects between the surface of the glass layer and the dielectric layer, wherein individual interconnects electrically couple individual TGVs to individual conductive pathways. In some embodiments, the interconnects include solder or liquid metal ink. In some embodiments, the interconnects include metal-metal bonds and dielectric-dielectric bonds.

公开(公告)号：US20250096053A1

公开(公告)日：2025-03-20

申请号：US18470645

申请日：2023-09-20

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Bohan Shan ,  Tarek A. Ibrahim ,  Srinivas V. Pietambaram ,  Gang Duan ,  Benjamin T. Duong ,  Suddhasattwa Nad

IPC: H01L23/15 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065

Abstract: A microelectronic assembly includes an embedded bridge die and a glass structure, such as glass patch, under the bridge die. The bridge die and the glass structure are embedded in a substrate. The assembly may further include two or more dies arranged over the substrate and coupled to the bridge die. The glass structure may include through-glass vias, and vias in the substrate below the glass structure are self-aligned to the through-glass vias. The glass structure may include an embedded passive device, such as an embedded inductor or capacitor.

公开(公告)号：US20250079266A1

公开(公告)日：2025-03-06

申请号：US18456615

申请日：2023-08-28

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Srinivas V. Pietambaram ,  Gang Duan ,  Jeremy Ecton

IPC: H01L23/482 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Embodiments of a microelectronic assembly comprise: a package substrate having a blind cavity between a first surface and a second opposing surface; a bridge die in the blind cavity, the blind cavity being open towards the first surface; and a plurality of integrated circuit (IC) dies coupled to the first surface and to the bridge die. The blind cavity has a floor and a plurality of sidewalls, at least one sidewall is at an obtuse angle to the floor, and the at least one sidewall is patterned with conductive traces.