公开(公告)号：US11527532B2

公开(公告)日：2022-12-13

申请号：US16419240

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L23/31 ,  H01L23/00 ,  H01L29/778 ,  H01L25/065

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor-based cascode arrangements that may simultaneously realize enhancement mode transistor operation and high voltage capability. In one aspect, an IC structure includes a source region, a drain region, an enhancement mode III-N transistor, and a depletion mode III-N transistor, where each of the transistors includes a first and a second source or drain (S/D) terminals. The transistors are arranged in a cascode arrangement in that the first S/D terminal of the enhancement mode III-N transistor is coupled to the source region, the second S/D terminal of the enhancement mode III-N transistor is coupled to the first S/D terminal of the depletion mode III-N transistor, and the second S/D terminal of the depletion mode III-N transistor is coupled to the drain region.

公开(公告)号：US11508812B2

公开(公告)日：2022-11-22

申请号：US16643446

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Pavel M. Agababov

IPC: H01L29/06 ,  H01L29/778 ,  H01L21/02

Abstract: Techniques related to forming low defect density III-N films, device structures, and systems incorporating such films are discussed. Such techniques include epitaxially growing a first crystalline III-N structure within an opening of a first dielectric layer and extending onto the first dielectric layer, forming a second dielectric layer over the first dielectric layer and laterally adjacent to a portion of the first structure, and epitaxially growing a second crystalline III-N structure extending laterally onto a region of the second dielectric layer.

公开(公告)号：US20220320350A1

公开(公告)日：2022-10-06

申请号：US17848275

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/20 ,  H01L29/778

Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

公开(公告)号：US11430873B2

公开(公告)日：2022-08-30

申请号：US16147707

申请日：2018-09-29

Applicant: Intel Corporation

Inventor： Walid Hafez ,  Han Wui Then ,  Sansaptak Dasgupta ,  Marko Radosavljevic ,  Paul Fischer

IPC: H01L29/40 ,  H01L21/768 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/20 ,  H01L29/778 ,  H01L29/423

Abstract: A device includes a first Group III-Nitride (III-N) material, a gate electrode above the III-N material, and the gate electrode. The device further includes a tiered field plate, suitable for increasing gate breakdown voltage with minimal parasitics. In the tiered structure, a first plate is on the gate electrode, the first plate having a second sidewall laterally beyond a sidewall of the gate, and above the III-N material by a first distance. A second plate on the first plate has a third sidewall laterally beyond the second sidewall and above the III-N material by a second distance, greater than the first. A source structure and a drain structure are on opposite sides of the gate electrode, where the source and drain structures each include a second III-N material.

公开(公告)号：US11342232B2

公开(公告)日：2022-05-24

申请号：US16016415

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Paul Fischer ,  Walid Hafez

IPC: H01L21/8252 ,  H01L27/06 ,  H01L27/02 ,  H01L29/872 ,  H01L21/02 ,  H01L29/778

Abstract: A diode is disclosed. The diode includes a semiconductor substrate, a hard mask formed above the substrate, vertically oriented components of a first material adjacent sides of the hard mask, and laterally oriented components of the first material on top of the hard mask. The laterally oriented components are oriented in a first direction and a second direction. The diode also includes a second material on top of the first material. The second material forms a Schottky barrier.

公开(公告)号：US11335801B2

公开(公告)日：2022-05-17

申请号：US16642866

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: A device including a III-N material is described. In an example, a device includes a first layer including a first group III-nitride (III-N) material and a polarization charge inducing layer, including a second III-N material, above the first layer. The device further includes a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The source structure and the drain structure both include a first portion adjacent to the first layer and a second portion above the first portion, the first portion includes a third III-N material with an impurity dopant, and the second portion includes a fourth III-N material, where the fourth III-N material includes the impurity dopant and further includes indium, where the indium content increases with distance from the first portion.

公开(公告)号：US11329132B2

公开(公告)日：2022-05-10

申请号：US16016406

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta ,  Paul Fischer ,  Walid Hafez

IPC: H01L29/15 ,  H01L29/423 ,  H01L29/08 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8252 ,  H01L21/306 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L29/20

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a superlattice that includes a plurality of layers of alternating materials above the substrate, where each of the plurality of layers corresponds to a threshold voltage, a gate trench extending into the superlattice to a predetermined one of the plurality of layers of the superlattice structure, and a high-k layer on the bottom and sidewall of the trench, the high-k layer contacting an etch stop layer of one of the plurality of layers of alternating materials. A gate is located in the trench on top of the high-k layer.

公开(公告)号：US20220093492A1

公开(公告)日：2022-03-24

申请号：US17025771

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Krishna Bharath ,  Han Wui Then ,  Kimin Jun ,  Aleksandar Aleksov ,  Mohammad Enamul Kabir ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/49 ,  H05K1/11 ,  H01L23/538 ,  H01L23/532

Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.

公开(公告)号：US11056449B2

公开(公告)日：2021-07-06

申请号：US16462726

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer

IPC: H01L23/48 ,  H01L23/58 ,  H01L21/02 ,  H01L29/20

Abstract: A guard ring structure includes a ring of semiconductor material disposed on a substrate. A conductive ring is disposed on the ring of semiconductor material. The conductive ring is interconnected by intervening vias. The guard ring structure may include a plurality of individual rings of the semiconductor material formed concentrically and in close proximity to one another on the substrate. A Guard ring structure is generally disposed around a periphery of a die containing integrated circuits that include transistors RF amplifiers and memory devices to reduce the impact of stresses arising from die sawing to separate individual die in a wafer.

公开(公告)号：US10930500B2

公开(公告)日：2021-02-23

申请号：US16431646

申请日：2019-06-04

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Benjamin Chu-Kung ,  Marko Radosavljevic ,  Sanaz K. Gardner ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L21/02 ,  H01L29/778 ,  H01L29/04 ,  H01L29/06 ,  H01L29/20 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/16 ,  H01L29/267 ,  H01L29/78 ,  H01L29/66

Abstract: III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.