公开(公告)号：US20190273133A1

公开(公告)日：2019-09-05

申请号：US16347110

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey ,  Glenn A. Glass ,  Van H. Le ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Willy Rachmady

IPC: H01L29/08 ,  H01L29/165 ,  H01L29/16 ,  H01L29/36 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L29/45 ,  H01L29/417 ,  H01L29/10

Abstract: Disclosed herein are transistor amorphous interlayer arrangements, and related methods and devices. For example, in some embodiments, transistor amorphous interlayer arrangement may include a channel material and a transistor source/drain stack. The transistor source/drain stack may include a transistor electrode material configured to be a transistor source/drain contact, i.e. either a source contact or a drain contact of the transistor, and a doped amorphous semiconductor material disposed between the transistor electrode material and the channel material.

公开(公告)号：US10347767B2

公开(公告)日：2019-07-09

申请号：US15570742

申请日：2015-06-16

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Ashish Agrawal

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06

Abstract: A subfin layer is deposited in a trench in an insulating layer on the substrate. A fin is deposited on the subfin layer. The fin has a top portion and opposing sidewalls. The fin comprises a first semiconductor material. The subfin layer comprises a III-V semiconductor material.

公开(公告)号：US10340374B2

公开(公告)日：2019-07-02

申请号：US15755450

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Sean T. Ma ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/775 ,  H01L29/201 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/06

Abstract: Monolithic FETs including a channel region of a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering the channel region, an impurity-doped compositionally graded semiconductor is grown, for example on at least a drain end of the channel region to introduce a carrier-blocking conduction band offset and/or a wider band gap within the drain region of the transistor. In some embodiments, the compositional grade induces a carrier-blocking band offset of at least 0.25 eV. The wider band gap and/or band offset contributes to a reduced gate induced drain leakage (GIDL). The impurity-doped semiconductor may be compositionally graded back down from the retrograded composition to a suitably narrow band gap material providing good ohmic contact. In some embodiments, the impurity-doped compositionally graded semiconductor growth is integrated into a gate-last, source/drain regrowth finFET fabrication process.

公开(公告)号：US10249490B2

公开(公告)日：2019-04-02

申请号：US15458897

申请日：2017-03-14

Applicant: Intel Corporation

Inventor： Niti Goel ,  Robert S. Chau ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Niloy Mukherjee ,  Nancy M. Zelick ,  Gilbert Dewey ,  Willy Rachmady ,  Marko Radosavljevic ,  Van H. Le ,  Ravi Pillarisetty ,  Sansaptak Dasgupta

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8252 ,  H01L27/092 ,  H01L29/06 ,  H01L29/165 ,  H01L29/205 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20

Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

公开(公告)号：US10141437B2

公开(公告)日：2018-11-27

申请号：US15626067

申请日：2017-06-16

Applicant: Intel Corporation

Inventor： Suman Datta ,  Mantu K. Hudait ,  Mark L. Doczy ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Justin K. Brask ,  Been-Yih Jin ,  Matthew V. Metz ,  Robert S. Chau

IPC: H01L29/778 ,  H01L29/15 ,  H01L29/205 ,  H01L29/51 ,  H01L27/092 ,  H01L29/66

Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.

公开(公告)号：US20170229543A1

公开(公告)日：2017-08-10

申请号：US15504280

申请日：2014-09-19

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Chandra S. Mohapatra ,  Tahir Ghani ,  Willy Rachmady ,  Gilbert Dewey ,  Matthew V. Metz ,  Jack T. Kavalieros

IPC: H01L29/10 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L29/1054 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: Transistor devices having indium gallium arsenide active channels, and processes for the fabrication of the same, that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium gallium arsenide material may be deposited in narrow trenches which may result in a fin that has indium rich surfaces and a gallium rich central portion. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous composition indium gallium arsenide active channels.

公开(公告)号：US20170194142A1

公开(公告)日：2017-07-06

申请号：US15464888

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Niti Goel ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L29/0607 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/785

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

公开(公告)号：US09698013B2

公开(公告)日：2017-07-04

申请号：US14908987

申请日：2013-09-04

Applicant: Intel Corporation

Inventor： Niloy Mukherjee ,  Niti Goel ,  Sanaz K. Gardner ,  Pragyansri Pathi ,  Matthew V. Metz ,  Sansaptak Dasgupta ,  Seung Hoon Sung ,  James M. Powers ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/267 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L21/02694 ,  H01L21/02381 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02609 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7848

Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.

公开(公告)号：US20170154981A1

公开(公告)日：2017-06-01

申请号：US15430348

申请日：2017-02-10

Applicant: Intel Corporation

Inventor： Niti Goel ,  Benjamin Chu-Kung ,  Sansaptak Dasgupta ,  Niloy Mukherjee ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Ravi Pillarisetty

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/84 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/76248 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/66795

Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystaline defects in the fins due to lattice mismatch in the layer interfaces.

公开(公告)号：US12288803B2

公开(公告)日：2025-04-29

申请号：US18540544

申请日：2023-12-14

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Sean T. Ma ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey

IPC: H01L29/06 ,  H01L29/205 ,  H01L29/423 ,  H01L29/78

Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).