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公开(公告)号：US10802567B2
公开(公告)日：2020-10-13
申请号：US15849836
申请日：2017-12-21
Applicant: Intel Corporation
Inventor： Nadav Bonen , Ron Gabor , Zeev Sperber , Vjekoslav Svilan , David N. Mackintosh , Jose A. Baiocchi Paredes , Naveen Kumar , Shantanu Gupta
IPC: G06F1/3234 , G06F1/3287 , G06F9/30 , G06F9/38
Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
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公开(公告)号：US10725849B2
公开(公告)日：2020-07-28
申请号：US16047638
申请日：2018-07-27
Applicant: Intel Corporation
Inventor： David Durham , Siddhartha Chhabra , Kai Cong , Ron Gabor
Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if an access request (e.g., a read or write request) to a memory location would result in an integrity failure and, if so determined, read previous data from the memory location, set an indicator to indicate the integrity failure, and store the previous data together with the indicator and previous authentication information. Other embodiments are disclosed and claimed.
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公开(公告)号：US10725755B2
公开(公告)日：2020-07-28
申请号：US15615798
申请日：2017-06-06
Applicant: Intel Corporation
Inventor： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffrey J. Cook , Omar M. Shaikh , Suresh Srinivas
Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
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公开(公告)号：US10521361B2
公开(公告)日：2019-12-31
申请号：US15904717
申请日：2018-02-26
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Ady Tal , Joseph Nuzman
Abstract: Memory corruption detection technologies are described. A method may store in a register an address of a memory corruption detection (MCD) table. The method receives, from an application, a memory store request to store data in a first portion of a contiguous memory block of a memory and sends, to the application, a fault message when a fault event associated with the first portion occurs in view of a protection mode of the first portion, wherein the protection mode indicates that the first portion is write protected.
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公开(公告)号：US20190004886A1
公开(公告)日：2019-01-03
申请号：US16123933
申请日：2018-09-06
Applicant: Intel Corporation
Inventor： Tomer Stark , Ady Tal , Ron Gabor
CPC classification number: G06F11/079 , G06F11/073 , G06F11/0751 , G06F11/0772 , G06F11/10 , G06F11/1064
Abstract: Memory corruption detection technologies are described. A processor core of a processor can receive a first pointer produced by a first memory access instruction of an application being executed by the processor. The first pointer includes a first memory address of a first memory object and a third metadata value and the memory address identifies a memory block in the first set of one or more contiguous memory blocks. The processor core compares the third metadata value to the first metadata value and communicates a memory corruption detection message to the application when the third metadata value does not match the first metadata value. The processor core provides the first memory object to the application when the third metadata value matches the first metadata value.
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Patent Agency Ranking
公开(公告)号：US20180181501A1
公开(公告)日：2018-06-28
申请号：US15904717
申请日：2018-02-26
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Ady Tal , Joseph Nuzman
Abstract: Memory corruption detection technologies are described. A method may store in a register an address of a memory corruption detection (MCD) table. The method receives, from an application, a memory store request to store data in a first portion of a contiguous memory block of a memory and sends, to the application, a fault message when a fault event associated with the first portion occurs in view of a protection mode of the first portion, wherein the protection mode indicates that the first portion is write protected.
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67.发明申请公开(公告)号：US20180004588A1
公开(公告)日：2018-01-04
申请号：US15708079
申请日：2017-09-18
Applicant: Intel Corporation
Inventor： Tomer Stark , Ady Tal , Ron Gabor , Joseph Nuzman
CPC classification number: G06F11/079 , G06F11/073 , G06F11/0751 , G06F11/0772 , G06F11/10 , G06F11/1064
Abstract: Memory corruption detection technologies are described. A processor can include a memory to store a memory corruption detection (MCD) table. A processor core of the processor can receive, from an application, an allocation request for an allocation of a memory object within a contiguous memory block in the memory. The processor core can allocate the contiguous memory block in view of a size of the memory object requested and write MCD meta-data into the MCD table, including a MCD identifier (ID) associated with the contiguous memory block and a MCD border value indicating a size of a memory region of the contiguous memory block.
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公开(公告)号：US09858140B2
公开(公告)日：2018-01-02
申请号：US14531498
申请日：2014-11-03
Applicant: Intel Corporation
Inventor： Ron Gabor , Raanan Sade , Joseph Nuzman
IPC: G06F11/10
CPC classification number: G06F11/10
Abstract: Systems and methods for memory corruption detection. An example processing system comprises a processing core including a register to store a base address of a memory corruption detection (MCD) table. The processing core is configured to validate a pointer referenced by a memory access instruction, by comparing a first value derived from a first portion of the pointer to a second value stored in the MCD table at an offset referenced by a second portion of the pointer.
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公开(公告)号：US20170371397A1
公开(公告)日：2017-12-28
申请号：US15647355
申请日：2017-07-12
Applicant: Intel Corporation
Inventor： Nadav Bonen , Ron Gabor , Zeev Sperber , Vjekoslav Svilan , David N. Mackintosh , Jose A. Baiocchi Paredes , Naveen Kumar , Shantanu Gupta
CPC classification number: G06F1/3243 , G06F1/3287 , G06F9/30083 , G06F9/3869 , G06F9/3885 , Y02B70/123 , Y02B70/126 , Y02D10/152 , Y02D10/171
Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.
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公开(公告)号：US20170185535A1
公开(公告)日：2017-06-29
申请号：US15460977
申请日：2017-03-16
Applicant: INTEL CORPORATION
Inventor： Tomer Stark , Ron Gabor , Ady Tal , Joseph Nuzman
CPC classification number: G06F12/1425 , G06F11/073 , G06F11/0751 , G06F11/0766 , G06F11/0772 , G06F11/0787 , G06F11/1666 , G06F12/0238 , G06F2201/80 , G06F2212/1032
Abstract: Memory corruption detection technologies are described. A system on a chip (SoC) may include a memory device and a memory controller. The memory device may store data from an application, wherein the memory device comprises a memory corruption detection (MCD) table. The memory controller may be coupled to the memory device. The memory controller may allocate a contiguous memory block in the memory and write a MCD word into the MCD table. The MCD word may include a write protection indicator that indicates a protection mode of a first portion of the contiguous memory block.
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