公开(公告)号：US20170025390A1

公开(公告)日：2017-01-26

申请号：US15286086

申请日：2016-10-05

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Richard Dewitt Crisp ,  Wael Zohni

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/4846 ,  H01L21/565 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/745 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/1184 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13624 ,  H01L2224/13655 ,  H01L2224/1369 ,  H01L2224/14051 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/32145 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/742 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/9202 ,  H01L2224/92142 ,  H01L2224/92143 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00

Abstract: A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later.

Abstract translation: 微电子结构包括在第一表面具有导电元件的半导体。 线接合具有接合到导电元件和远离基座的自由端的基部，自由端远离基板和基部并且包括端面。 线接合限定其基端和端面之间的边缘表面。 顺应性材料层沿着线的第一部分中的边缘表面延伸，至少邻近其底部，并且填充引线接合的第一部分之间的空间，使得引线接合的第一部分通过顺应性 材料层。 线接合的第二部分由邻近端表面的端表面和边缘表面的部分限定，其从较柔性的第三表面延伸。

公开(公告)号：US09530458B2

公开(公告)日：2016-12-27

申请号：US14962734

申请日：2015-12-08

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: G11C5/02 ,  H01L25/065 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18

CPC classification number: G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/24 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/06165 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45014 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/9202 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane.

公开(公告)号：US20160268187A1

公开(公告)日：2016-09-15

申请号：US15165323

申请日：2016-05-26

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: H01L23/498 ,  H01L27/108 ,  H01L23/31

CPC classification number: H01L23/49838 ,  G11C5/04 ,  G11C5/063 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/52 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L27/108 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06156 ,  H01L2224/06164 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81447 ,  H01L2224/81805 ,  H01L2224/9202 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region.

公开(公告)号：US20160190100A1

公开(公告)日：2016-06-30

申请号：US15060240

申请日：2016-03-03

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  G11C5/063 ,  H01L23/12 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/1715 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid.

公开(公告)号：US20160172332A1

公开(公告)日：2016-06-16

申请号：US15050070

申请日：2016-02-22

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Wael Zohni ,  Richard Dewitt Crisp ,  Ilyas Mohammed

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L23/481 ,  G11C5/04 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49838 ,  H01L23/538 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/09 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/108 ,  H01L2224/0401 ,  H01L2224/061 ,  H01L2224/091 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15786 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/301 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals.

公开(公告)号：US09368477B2

公开(公告)日：2016-06-14

申请号：US13841052

申请日：2013-03-15

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Belgacem Haba ,  Wael Zohni

IPC: H01L23/48 ,  H01L25/065 ,  G11C5/06 ,  H05K1/11 ,  H01L23/498 ,  H01L23/538 ,  H05K1/02 ,  H01L25/10

CPC classification number: H01L25/0652 ,  G11C5/063 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/5389 ,  H01L25/0655 ,  H01L25/105 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/111 ,  H05K2201/10159 ,  H01L2924/00

Abstract: A circuit panel can include contacts exposed at a connection site of a major surface thereof and configured to be coupled to terminals of a microelectronic package. The connection site can define a peripheral boundary on the major surface surrounding a group of the contacts that is configured to be coupled to a single microelectronic package. The group of contacts can include first, second, third, and fourth sets of first contacts. Signal assignments of the first and third sets of first contacts can be symmetric about a theoretical plane normal to the major surface with signal assignments of the respective second and fourth sets of first contacts. Each of the sets of first contacts can be configured to carry identical signals. Each of the sets of first contacts can be configured to carry address information sufficient to specify a location within a memory storage array of the microelectronic package.

Abstract translation: 电路板可以包括暴露在其主表面的连接位置并被配置为耦合到微电子封装的端子的触点。 连接部位可以在被配置为耦合到单个微电子封装的一组触点周围的主表面上限定外围边界。 该组联系人可以包括第一，第二，第三和第四组第一联系人。 第一和第三组第一触点的信号分配可以相对于主表面垂直的理论平面对称，具有相应的第二和第四组第一触点的信号分配。 可以将每组第一个触点设置为携带相同的信号。 可以将每组第一触点组配置为承载足以指定微电子封装的存储器存储阵列内的位置的地址信息。

公开(公告)号：US09287216B2

公开(公告)日：2016-03-15

申请号：US14472991

申请日：2014-08-29

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Wael Zohni ,  Richard Dewitt Crisp ,  Ilyas Mohammed

IPC: H01L23/538 ,  H01L25/065 ,  G11C5/04 ,  H01L23/12 ,  H01L27/108 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18 ,  H01L23/13 ,  H01L23/36 ,  H01L23/498

CPC classification number: H01L23/481 ,  G11C5/04 ,  H01L23/12 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49838 ,  H01L23/538 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/09 ,  H01L24/29 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/108 ,  H01L2224/0401 ,  H01L2224/061 ,  H01L2224/091 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15786 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/301 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals.

Abstract translation: 微电子封装可以包括具有第一和第二相对表面的衬底，至少两对微电子元件和在第二表面处暴露的多个端子。 每对微电子元件可以包括上微电子元件和下微电子元件。 这些微电子元件对可以在平行于衬底的第一表面的水平方向上彼此完全间隔开。 每个下部微电子元件可以具有面向基板的第一表面的前表面和在前表面处的多个触点。 每个上部微电子元件的表面可以至少部分地覆盖在其对中的下部微电子元件的后表面。 微电子封装还可以包括从每个下部微电子元件的至少一些触点延伸到至少一些端子的电连接。

公开(公告)号：US20160035656A1

公开(公告)日：2016-02-04

申请号：US14775119

申请日：2014-03-10

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Richard Dewitt Crisp ,  Wael Zohni

IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/49811 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package (10) can include lower and upper package faces (11, 12), lower terminals (25) at the lower package face, upper terminals (45) at the upper package face, first and second microelectronic elements (30) each having memory storage array function, and conductive interconnects (15) each electrically connecting at least one lower terminal with at least one upper terminal. The conductive interconnects (15) can include first conductive interconnects (15a) configured to carry address in formation, signal assignments of a first set (70a) of the first interconnects having (180) rotational symmetry about a theoretical rotational axis (29) with signal assignments of a second set (70b) of first interconnects. The conductive interconnects (15) can also include second conductive interconnects (15b) configured to carry data information, the position of each second conductive interconnect having (180) rotational symmetry about the rotational axis (29) with a position of a corresponding no-connect conductive interconnect (15d).

Abstract translation: 微电子封装（10）可以包括位于下封装面的下封装面（11,12），下端子（25），上封装面上的上端子（45），第一和第二微电子元件 具有存储器阵列功能，以及每个电连接至少一个下端子与至少一个上端子的导电互连件（15）。 导电互连（15）可以包括被配置为承载形成地址的第一导电互连（15a），具有（180）旋转对称的第一互连的第一组（70a）与理论旋转轴（29）的信号分配与信号 第一组互连（70b）的分配。 导电互连（15）还可以包括被配置为承载数据信息的第二导电互连（15b），具有（180）围绕旋转轴线（29）的（180）旋转对称的每个第二导电互连的位置具有对应的不连接 导电互连（15d）。

公开(公告)号：US20150214178A1

公开(公告)日：2015-07-30

申请号：US14669540

申请日：2015-03-26

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba

IPC: H01L23/00

CPC classification number: H01L24/49 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/02375 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/0901 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/49052 ,  H01L2224/4912 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19107 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor unit includes a chip having left and right columns of contacts at its front surface. Interconnect pads are provided overlying the front surface of the chip and connected to at least some of the contacts as, for example, by traces or by arrangements including wire bonds. The interconnect pads alone, or the interconnect pads and some of the contacts, provide an array of external connection elements. This array includes some reversal pairs of external connection elements in which the external connection element connected to or incorporating the right contact is disposed to the left of the external connection element incorporating or connected to the left contact. Such a unit may be used in a multi-chip package such as a two-chip package having a first chip facing upwardly and a second chip facing downwardly towards a package substrate, disposed below the chips. The reversed connections simplify routing, particularly where corresponding contacts of the two chips are to be connected to common terminals on the package substrate.

Abstract translation: 半导体单元包括在其前表面具有左列和右列触点的芯片。 互连焊盘被提供在芯片的前表面上并且连接到至少一些触点，例如通过迹线或包括引线键合的布置。 单独的互连焊盘或互连焊盘和一些触点提供外部连接元件的阵列。 该阵列包括一些外部连接元件的反转对，其中连接到或结合右触点的外部连接元件设置在并入或连接到左触点的外部连接元件的左侧。 这种单元可以用于多芯片封装，例如设置在芯片下方的具有面向上的第一芯片的双芯片封装和朝向封装基板的向下的第二芯片。 反向连接简化了路由，特别是在两个芯片的相应触点连接到封装基板上的公共端子的情况下。

公开(公告)号：US09070423B2

公开(公告)日：2015-06-30

申请号：US14075020

申请日：2013-11-08

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Yong Chen ,  Belgacem Haba ,  Wael Zohni ,  Zhuowen Sun

IPC: G11C5/00 ,  G11C5/02 ,  G11C8/00 ,  G11C8/18 ,  H01L23/00 ,  H01L25/065 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12 ,  H01L23/538

CPC classification number: G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C8/12 ,  G11C11/408 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.

Abstract translation: 微电子封装可以包括具有第一和第二表面的第一表面和第二表面的支撑元件以及与第一表面或第二表面的第一和第二堆叠的微电子元件，以及与第二表面电连接的第二表面的端子与微电子元件电耦合。 第二表面可以具有包括第二表面的南部和西部边缘的整个长度的西南区域，并且在从每个距离的南部和西部边缘的正交方向上分别向第二表面的北部和东部边缘延伸。 终端可以包括在第二表面的西南区域的第一终端，第一终端被配置为携带可用于微电子封装内的电路的地址信息，以从存储器存储阵列的所有可寻址的存储器位置中确定可寻址存储器位置 第一或第一微电子元件中的至少一个。