公开(公告)号：US20220367691A1

公开(公告)日：2022-11-17

申请号：US17660729

申请日：2022-04-26

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Akihiro HANADA ,  Takaya TAMARU

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/4757 ,  H01L21/4763 ,  H01L21/426 ,  H01L29/786

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

公开(公告)号：US20220310713A1

公开(公告)日：2022-09-29

申请号：US17699250

申请日：2022-03-21

Applicant: Japan Display Inc.

Inventor： Hayata AOKI ,  Masashi TSUBUKU ,  Toshinari SASAKI

IPC: H01L27/32 ,  H01L51/52

Abstract: According to one embodiment, a display device includes a first area including a pixel and a second area different from the first area, wherein the pixel includes a pixel electrode, an organic material layer including a light-emitting layer, a first common electrode, and a second common electrode having transmittance higher than that of the first insulating layer, the second area is an area not overlapping the light-emitting layer in plan view, the second area is a transparent area, and the second area does not comprise the first common electrode provided therein.

公开(公告)号：US20220190164A1

公开(公告)日：2022-06-16

申请号：US17549882

申请日：2021-12-14

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Kentaro MIURA ,  Toshinari SASAKI ,  Takeshi SAKAI ,  Akihiro HANADA ,  Masashi TSUBUKU

IPC: H01L29/786 ,  H01L29/423

Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor. The oxide semiconductor includes a first edge portion and a second edge portion intersecting a gate electrode, a first area overlapping the gate electrode, a second area along the first edge portion, a third area along the second edge portion, a fourth area the first edge portion, a fifth area along the second edge portion, a sixth area surrounded by the first area, the second area and the third area, and a seventh area surrounded by the first area, the fourth area and the fifth area. The first area, the second area and the third area, the fourth area and the fifth area have a higher resistivity than those of the sixth area and the seventh area.

公开(公告)号：US20220077344A1

公开(公告)日：2022-03-10

申请号：US17527192

申请日：2021-11-16

Applicant: Japan Display Inc.

Inventor： Masashi TSUBUKU ,  Takanori TSUNASHIMA ,  Marina MOCHIZUKI

IPC: H01L31/12 ,  H01L31/101 ,  G06F1/16

Abstract: A photo sensor circuit includes: a photo transistor; a first switching transistor; a second switching transistor; and a capacitance element. The photo transistor includes: a gate connected to a first wiring; a source connected to a second wiring; and a drain. The first switching transistor includes: a gate connected to a third wiring; a source connected to a fourth wiring; and a drain connected to the drain of the photo transistor. The capacitance element includes: a first terminal connected to the drain of the photo transistor; and a second terminal connected to the source of the first switching transistor. The second switching transistor includes: a gate connected to a gate line; a source connected to a signal line; and a drain connected to the first terminal of the capacitance element. The photo transistor, first switching transistor, and second transistor each include an oxide semiconductor layer as a channel layer.

公开(公告)号：US20220004071A1

公开(公告)日：2022-01-06

申请号：US17448419

申请日：2021-09-22

Applicant: Japan Display Inc.

Inventor： Masashi TSUBUKU ,  Makoto UCHIDA ,  Takashi NAKAMURA

IPC: G02F1/1362 ,  G02F1/1368

Abstract: A display device includes: a display portion, a first transistor arranged in the display portion and including a first semiconductor layer, a second transistor arranged adjacent to the first transistor in the display portion and including a second semiconductor layer arranged in a different layer from the first semiconductor layer, a first signal line connected to the first transistor, a second signal lime connected to the second transistor, a gate line overlapping the first transistor and the second transistor, and a display element arranged on the first transistor and the second transistor.

公开(公告)号：US20220004039A1

公开(公告)日：2022-01-06

申请号：US17447740

申请日：2021-09-15

Applicant: Japan Display Inc.

Inventor： Masashi TSUBUKU ,  Takeshi SAKAI ,  Tatsuya TODA

IPC: G02F1/1368 ,  H01L27/32 ,  H01L51/56

Abstract: A display device comprising a transistor and a display element over the transistor, wherein the transistor includes a gate electrode on an insulating surface, a gate insulating layer on the gate electrode, and source/drain electrodes on the oxide semiconductor layer and the gate insulating layer, each including a first conductive layer containing nitrogen and a second conductive layer on the first conductive layer, and an insulating layer contains oxygen on the oxide semiconductor layer and the source/drain electrodes.

公开(公告)号：US20210210524A1

公开(公告)日：2021-07-08

申请号：US17209376

申请日：2021-03-23

Applicant: Japan Display Inc.

Inventor： Tatsuya TODA ,  Masashi TSUBUKU

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/45 ,  H01L29/786 ,  H01L21/02 ,  H01L21/4763 ,  H01L29/66

Abstract: To reduce degradation of characteristics and reliability of a transistor including an oxide semiconductor as an active layer. A thin film transistor comprising: an active layer formed of an oxide semiconductor including at least indium and gallium; an electrode layer including an aluminum layer and partially formed on the active layer; and an interlayer insulating layer formed on the active layer, wherein a peak value of chlorine concentration at an interface between the interlayer insulating layer and the active layer is equal to or less than 2.0×1019 [atoms/cm3], and a peak value of aluminum concentration at an interface between the interlayer insulating layer and the active layer is equal to or less than 1.0×1020 [atoms/cm3].

公开(公告)号：US20210151604A1

公开(公告)日：2021-05-20

申请号：US17162340

申请日：2021-01-29

Applicant: Japan Display Inc.

Inventor： Takashi OKADA ,  Masashi TSUBUKU

IPC: H01L29/786

Abstract: A thin film transistor comprising an active layer made of an oxide semiconductor containing at least indium and gallium; an electrode layer partially formed on the active layer; an oxide film insulating layer formed on the active layer and the electrode layer; and a nitride film insulating layer formed on the oxide film insulating layer. The thin film transistor further comprises an oxygen diffusion-inhibiting film partially overlapping with the active layer in a plan view between the oxide film insulating layer and the nitride film insulating layer.

公开(公告)号：US20250113542A1

公开(公告)日：2025-04-03

申请号：US18887091

申请日：2024-09-17

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Kentaro MIURA ,  Akihiro HANADA ,  Takaya TAMARU ,  Masahiro WATABE

IPC: H01L29/786

Abstract: A semiconductor device comprises a first insulating layer; an oxide semiconductor layer having a polycrystalline structure on the first insulating layer; a gate insulating layer on the semiconductor oxide layer; a buffer layer on the gate insulating layer; a gate wiring on the buffer layer; and a second insulating layer on the gate wiring. The oxide semiconductor layer has a first region, a second region and a third region aligned toward a first direction. An electrical resistivity of the second region is higher than an electrical resistivity of the first region and lower than an electrical resistivity of the third region. A sheet resistance of the third region is less than 1000 ohm/square.

公开(公告)号：US20250063761A1

公开(公告)日：2025-02-20

申请号：US18934397

申请日：2024-11-01

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

IPC: H01L29/786 ,  G02F1/1368 ,  H01L29/66 ,  H10K59/121

Abstract: A semiconductor device includes a metal oxide layer containing aluminum over an insulating surface and an oxide semiconductor layer over the metal oxide layer. The oxide semiconductor layer includes a first crystal region in contact with the metal oxide layer and a second crystal region in contact with the first crystal region and having a larger area than the first crystal region in a cross-sectional view of the oxide semiconductor layer. The first crystal region and the second crystal region differ from each other in at least one of a crystal structure and a crystal orientation.