公开(公告)号：US20240332428A1

公开(公告)日：2024-10-03

申请号：US18617858

申请日：2024-03-27

Applicant: Japan Display Inc.

Inventor： Masahiro WATABE ,  Masashi TSUBUKU ,  Hajime WATAKABE ,  Toshinari SASAKI ,  Marina MOCHIZUKI ,  Takaya TAMARU ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L27/1248 ,  H01L29/42384

Abstract: A semiconductor device comprises a first insulating layer; a metal oxide layer mainly composed of aluminum on the first insulating layer; an oxide semiconductor layer having a polycrystalline structure on the metal oxide layer; a gate insulating layer on the oxide semiconductor layer; a gate electrode on the gate insulating layer; and a second insulating layer on the gate electrode. The metal oxide layer and the oxide semiconductor layer are both patterned, and the oxide semiconductor layer has a first region in contact with the gate insulating layer and a second region continuous with the first region in a first direction and in contact with the gate insulating layer and the second insulating layer.

公开(公告)号：US20240290861A1

公开(公告)日：2024-08-29

申请号：US18435094

申请日：2024-02-07

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Masahiro WATABE

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/4908 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device according to an embodiment includes: a first gate electrode; a first insulating layer on the first gate electrode; an oxide semiconductor layer on the first insulating layer; a second insulating layer on the oxide semiconductor layer; and a second gate electrode on the second insulating layer. The first insulating layer includes a first layer including silicon and nitrogen, a second layer including silicon and oxygen, and a third layer including aluminum and oxygen. A thickness of the first layer is 10 nm or more and 190 nm or less. A thickness of the second layer is 10 nm or more and 100 nm or less. A total thickness of the first layer and the second layer is 200 nm or less. A thickness of the third layer 1 nm or more and 10 nm or less.

公开(公告)号：US20240176196A1

公开(公告)日：2024-05-30

申请号：US18508246

申请日：2023-11-14

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

IPC: G02F1/1362 ,  G02F1/1368 ,  G06F3/044

CPC classification number: G02F1/136227 ,  G02F1/136286 ,  G02F1/13685 ,  G06F3/044

Abstract: A display device includes a plurality of pixel electrodes each connected to a semiconductor device, a plurality of common electrodes each disposed opposite to a part of the plurality of pixel electrodes, and a plurality of common wirings each connected to the plurality of common electrodes. The semiconductor device includes an oxide semiconductor layer having a polycrystalline structure, and at least a part of each common wiring is composed of the oxide semiconductor layer. Each common electrode may be located across a plurality of pixel electrodes.

公开(公告)号：US20240113228A1

公开(公告)日：2024-04-04

申请号：US18479934

申请日：2023-10-03

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Akihiro HANADA ,  Takaya TAMARU

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/425 ,  H01L21/4757 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/47576 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78633 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A semiconductor device according to an embodiment includes: an oxide insulating layer; an oxide semiconductor layer; a gate electrode; a gate insulating layer; and a first insulating layer, wherein the semiconductor device is divided into a first to a third regions, a thickness of the gate insulating layer in the first region is 200 nm or more, the gate electrode contacts the first insulating layer in the first region, the oxide semiconductor layer contacts the first insulating layer in the second region, an amount of impurities contained in the oxide semiconductor layer in the second region is greater than an amount of impurities contained in the oxide semiconductor layer in the first region, and an amount of impurities contained in the oxide insulating layer in the third region is greater than an amount of impurities contained in the oxide insulating layer in the second region.

公开(公告)号：US20240113227A1

公开(公告)日：2024-04-04

申请号：US18476910

申请日：2023-09-28

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Akihiro HANADA ,  Takaya TAMARU

IPC: H01L29/786 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L29/42384

Abstract: A method for manufacturing semiconductor device according to an embodiment includes: forming an oxide semiconductor layer above a substrate; forming a gate insulating layer above the oxide semiconductor layer; forming a metal oxide layer containing aluminum as a main component above the gate insulating layer; performing a heat treatment in a state where the metal oxide layer is formed above the gate insulating layer; removing the metal oxide layer after the heat treatment; and forming a gate electrode above the gate insulating layer.

公开(公告)号：US20240088302A1

公开(公告)日：2024-03-14

申请号：US18465251

申请日：2023-09-12

Applicant: Japan Display Inc.

Inventor： Takaya TAMARU ,  Masashi TSUBUKU ,  Hajime WATAKABE ,  Toshinari SASAKI

IPC: H01L29/786

CPC classification number: H01L29/7869

Abstract: A semiconductor device according to an embodiment includes: a substrate; a metal oxide layer arranged above the substrate and having aluminum as the main component of the metal oxide layer; an oxide semiconductor layer arranged above the metal oxide layer; a gate electrode facing the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein a thickness of the metal oxide layer is 1 nm or more and 4 nm or less.

公开(公告)号：US20240021695A1

公开(公告)日：2024-01-18

申请号：US18346280

申请日：2023-07-03

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU

IPC: H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/4908 ,  H01L29/7869 ,  H01L29/66969 ,  H01L29/401 ,  H01L21/425

Abstract: A semiconductor device includes a oxide semiconductor layer provided on an insulating surface and having a channel area, a source area and a drain area sandwiching the channel area, a gate electrode opposite the channel area, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, wherein the gate electrode is an oxide conductive layer having the same composition as the oxide semiconductor layer, and the oxide conductive layer includes the same impurity element as the source area and the drain area.

公开(公告)号：US20220216281A1

公开(公告)日：2022-07-07

申请号：US17570396

申请日：2022-01-07

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Toshinari SASAKI ,  Ryo ONODERA

IPC: H01L27/32

Abstract: According to one embodiment, in a first concentration of an impurity element contained in a first impurity region, a second concentration of the impurity element contained in a second impurity region, a third concentration of the impurity element contained in a third impurity region, and a fourth concentration of the impurity element contained in a high-concentration impurity region, the third concentration is equal to the fourth concentration, the third concentration is higher than the first concentration, and the first concentration is higher than the second concentration.

公开(公告)号：US20220013668A1

公开(公告)日：2022-01-13

申请号：US17483836

申请日：2021-09-24

Applicant: Japan Display Inc.

Inventor： Tatsuya TODA ,  Masashi TSUBUKU ,  Toshinari SASAKI

IPC: H01L29/786 ,  H01L27/12 ,  G01N23/20091

Abstract: A semiconductor device includes an oxide semiconductor layer including indium, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, and a first electrode arranged above the oxide semiconductor layer and being in contact with the oxide semiconductor layer from above the oxide semiconductor layer. The indium is unevenly distributed in an unevenly distributed region among the oxide semiconductor layer. The unevenly distributed region overlaps with the first conductive layer in a planar view.

公开(公告)号：US20180331127A1

公开(公告)日：2018-11-15

申请号：US15953614

申请日：2018-04-16

Applicant: Japan Display Inc.

Inventor： Toshinari SASAKI ,  Marina SHIOKAWA

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/127 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78633 ,  H01L29/7869

Abstract: A semiconductor device including a substrate, a first insulating layer above the substrate, a first transistor including a first oxide semiconductor layer above the first insulating layer, and a second transistor including a second oxide semiconductor layer above the first insulating layer, a composition of the second oxide semiconductor layer being different from a composition of the first oxide semiconductor layer.