公开(公告)号：US07888260B2

公开(公告)日：2011-02-15

申请号：US12829856

申请日：2010-07-02

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L21/44

CPC classification number: H01L24/16 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/36 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/14131 ,  H01L2224/16 ,  H01L2224/73104 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00

Abstract: A semiconductor device with its package size close to its chip size has a stress absorbing layer, allows a patterned flexible substrate to be omitted, and allows a plurality of components to be fabricated simultaneously. There is: a step of forming electrodes (12) on a wafer (10); a step of providing a resin later (14) as a stress relieving layer on the wafer (10), avoiding the electrodes (12); a step of forming a chromium layer (16) as wiring from electrodes (12) over the resin layer (14); and step of forming solder balls as external electrodes on the chromium layer (16) over the resin layer (14); and a step of cutting the wafer (10) into individual semiconductor chips; in the steps of forming the chromium layer (16) and solder balls, metal thin film fabrication technology is used during the wafer process.

Abstract translation: 其封装尺寸接近其芯片尺寸的半导体器件具有应力吸收层，允许省略图案化的柔性衬底，并且允许同时制造多个部件。 存在：在晶片（10）上形成电极（12）的步骤; 提供稍后的树脂（14）作为晶片（10）上的应力消除层的步骤，避免电极（12）; 从所述树脂层（14）上的电极（12）形成作为布线的铬层（16）的步骤; 以及在所述树脂层（14）上的所述铬层（16）上形成焊球作为外部电极的步骤; 以及将晶片（10）切割成单独的半导体芯片的步骤; 在形成铬层（16）和焊球的步骤中，在晶片工艺中使用金属薄膜制造技术。

公开(公告)号：US07863529B2

公开(公告)日：2011-01-04

申请号：US12236575

申请日：2008-09-24

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L23/02 ,  H05K5/06

CPC classification number: H03H9/1092 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/16225 ,  H01L2924/15311 ,  H03H9/1021 ,  H01L2924/00014

Abstract: An electronic component includes: a first substrate; a second substrate; a sealing member surrounding a sealing space formed between the first substrate and the second substrate; and a functional element at least a part of which is disposed in the sealing space. In the electronic component, the sealing member includes a core part formed on the first substrate and having elasticity and a metal film formed on a surface of the core part, and the metal film is bonded to the second substrate.

Abstract translation: 电子部件包括：第一基板; 第二基板; 围绕形成在所述第一基板和所述第二基板之间的密封空间的密封构件; 以及功能元件，其至少一部分设置在密封空间中。 在电子部件中，密封部件包括形成在第一基板上并且具有弹性的芯部和形成在芯部的表面上的金属膜，并且金属膜接合到第二基板。

公开(公告)号：US07851912B2

公开(公告)日：2010-12-14

申请号：US12719234

申请日：2010-03-08

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L21/00

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device including: a semiconductor chip; a plurality of electrodes formed on the semiconductor chip and arranged along one side of the semiconductor chip; a resin protrusion formed on the semiconductor chip and extending in a direction which intersects the side; and a plurality of electrical connection sections formed on the resin protrusion and electrically connected to the respective electrodes.

公开(公告)号：US07760512B2

公开(公告)日：2010-07-20

申请号：US11440377

申请日：2006-05-24

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H05K7/00

CPC classification number: H01L23/5223 ,  H01L23/3114 ,  H01L23/49822 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02351 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05557 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/05599

Abstract: An electronic board includes a substrate on which is formed an electronic circuit having a connection terminal; a stress-relaxation layer formed on the substrate; a rearrangement wiring for the connection terminal disposed at a top side of the stress-relaxation layer; and a capacitor. The capacitor has a first electrode that is disposed between the substrate and the stress-relaxation layer, a second electrode that is disposed at the top side of the stress-relaxation layer, and a dielectric material that is disposed between the first electrode and the second electrode. The first electrode and/or the second electrode has a corrugated surface facing the dielectric material.

Abstract translation: 电子板包括：基板，其上形成有具有连接端子的电子电路; 形成在所述基板上的应力松弛层; 用于连接端子的布置布置在应力松弛层的顶侧; 和电容器。 电容器具有设置在基板和应力松弛层之间的第一电极，设置在应力松弛层的顶侧的第二电极和布置在第一电极和第二电极之间的电介质材料 电极。 第一电极和/或第二电极具有面向电介质材料的波纹状表面。

公开(公告)号：US07659142B2

公开(公告)日：2010-02-09

申请号：US12219833

申请日：2008-07-29

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/485 ,  H01L23/488

CPC classification number: H01L23/3107 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/051 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is formed; an external electrodes formed on the conductive foil; intermediate layer formed between the passivation film and the conductive foil to support the conductive foil; and wires electrically connecting the electrodes to the conductive foil; wherein a depression tapered in a direction from the conductive foil to the passivation film if formed under a part of the conductive foil that includes the connection with the external electrodes.

Abstract translation: 一种半导体器件，包括：具有多个电极的半导体元件; 在避免每个电极的至少一部分的区域中形成在半导体元件上的钝化膜; 以与形成有钝化膜的表面成一定距离设置的导电箔; 形成在导电箔上的外部电极; 形成在钝化膜和导电箔之间的中间层以支撑导电箔; 以及将电极与导电箔电连接的导线; 如果形成在包括与外部电极的连接的导电箔的一部分下方，则在从导电箔到钝化膜的方向上渐缩的凹陷。

公开(公告)号：US07564142B2

公开(公告)日：2009-07-21

申请号：US11716568

申请日：2007-03-12

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L23/28

CPC classification number: H01L24/25 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/24 ,  H01L24/29 ,  H01L24/82 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/25175 ,  H01L2224/2518 ,  H01L2224/29 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82007 ,  H01L2224/82102 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: An electronic device includes: a substrate on which an interconnect pattern is formed; a chip component having a first surface on which an electrode is formed and a second surface opposite to the first surface, the chip component being mounted in such a manner that the second surface faces the substrate; an insulating section formed of a resin and provided adjacent to the chip component; and an interconnect which is formed to extend from above the electrode, over the insulating section and to above the interconnect pattern.

Abstract translation: 电子设备包括：其上形成有互连图案的基板; 芯片部件，其具有形成有电极的第一表面和与第一表面相对的第二表面，芯片部件以第二表面面向基板的方式安装; 绝缘部，由树脂构成，与所述芯片部件相邻设置; 以及互连，其形成为从电极的上方延伸穿过绝缘部分并且在互连图案之上。

公开(公告)号：US20090114441A1

公开(公告)日：2009-05-07

申请号：US12236575

申请日：2008-09-24

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L23/28

CPC classification number: H03H9/1092 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/16225 ,  H01L2924/15311 ,  H03H9/1021 ,  H01L2924/00014

Abstract: An electronic component includes: a first substrate; a second substrate; a sealing member surrounding a sealing space formed between the first substrate and the second substrate; and a functional element at least a part of which is disposed in the sealing space. In the electronic component, the sealing member includes a core part formed on the first substrate and having elasticity and a metal film formed on a surface of the core part, and the metal film is bonded to the second substrate.

Abstract translation: 电子部件包括：第一基板; 第二基板; 围绕形成在所述第一基板和所述第二基板之间的密封空间的密封构件; 以及功能元件，其至少一部分设置在密封空间中。 在电子部件中，密封部件包括形成在第一基板上并且具有弹性的芯部和形成在芯部的表面上的金属膜，并且金属膜接合到第二基板。

公开(公告)号：US07348263B2

公开(公告)日：2008-03-25

申请号：US11362591

申请日：2006-02-24

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L21/78 ,  H01L21/46 ,  H01L21/301 ,  H01L21/00 ,  H01L21/82

CPC classification number: H03H3/10 ,  B81B7/0048 ,  B81C2203/0109 ,  H01L21/563 ,  H01L2224/73204 ,  H03H9/0552 ,  H03H9/1071

Abstract: A manufacturing method for electronic device, includes: preparing a first substrate having a plurality of first regions; preparing a second substrate having a plurality of second regions; facing the first region and the second region each other, and connecting the first substrate and the second substrate while disposing at least a part of a functional element within a space between the first region and the second region; obtaining a plurality of first divisional substrates by cutting the first substrate at each of the first regions, after the connecting of the first substrate and the second substrate; forming a sealing film covering the plurality of the first divisional substrates on the second substrate, after cutting the first substrate; obtaining a plurality of second divisional substrates by cutting the second substrate at each of the second regions, after forming the sealing film; and obtaining a plurality of individual electronic devices.

Abstract translation: 一种电子设备的制造方法，包括：准备具有多个第一区域的第一基板; 制备具有多个第二区域的第二基板; 面对所述第一区域和所述第二区域，并且在所述第一区域和所述第二区域之间的空间内设置功能元件的至少一部分的同时连接所述第一基板和所述第二基板; 在第一基板和第二基板的连接之后，通过在每个第一区域处切割第一基板来获得多个第一分割基板; 在切割第一基板之后，形成覆盖第二基板上的多个第一分割基板的密封膜; 在形成密封膜之后，通过在每个第二区域切割第二基板来获得多个第二分割基板; 并获得多个单独的电子设备。

公开(公告)号：US07342179B2

公开(公告)日：2008-03-11

申请号：US11024992

申请日：2004-12-29

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H05K1/16

CPC classification number: H01L24/81 ,  B82Y30/00 ,  H01L24/11 ,  H01L2224/11332 ,  H01L2224/13099 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H05K3/102 ,  H05K3/321 ,  H05K2201/0257 ,  H05K2201/10674

Abstract: An electronic device includes a plurality of components, nanoparticles to bond the components, and a receiving layer for holding the nanoparticles, the receiving layer being disposed on at least one of the bonded components. The electronic device may further include an electrode disposed on at least one of the plurality of components. The receiving layer is disposed on the surface of the electrode. Conductive particles etc. are mixed in the receiving layer.

Abstract translation: 电子器件包括多个组分，用于结合组件的纳米颗粒和用于保持纳米颗粒的接收层，接收层设置在至少一个接合部件上。 电子设备还可以包括设置在多个部件中的至少一个上的电极。 接收层设置在电极的表面上。 导电粒子等在接收层中混合。

公开(公告)号：US07320902B2

公开(公告)日：2008-01-22

申请号：US10788447

申请日：2004-03-01

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L21/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L29/0657 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24998 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82007 ,  H01L2224/82102 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An external terminal is formed on an interconnect pattern formed on a substrate by using a soldering material. Subsequently, a chip component having an electrode is mounted on the substrate. An interconnect for electrically connecting the electrode and the interconnect pattern is formed at a temperature lower than a melting point of the soldering material.

Abstract translation: 外部端子通过使用焊接材料形成在形成在基板上的布线图案上。 随后，将具有电极的芯片部件安装在基板上。 在低于焊接材料的熔点的温度下形成用于电连接电极和互连图案的互连。