公开(公告)号：US12119065B2

公开(公告)日：2024-10-15

申请号：US17709762

申请日：2022-03-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiaochen Zhu ,  Lito De La Rama ,  Yi Song ,  Jiacen Guo ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  H01L25/065 ,  H10B43/27

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C11/5671 ,  G11C16/14 ,  G11C16/3459 ,  H01L25/0657 ,  H01L2225/06562 ,  H10B43/27

Abstract: A non-volatile memory system limits the amount of programming for a first type of group of non-volatile memory cells based on a first parameter such that a maximum number of programming pulses applied to the first type of group of non-volatile memory cells to program to the last data state after the first type of group of non-volatile memory cells completed programming to the other data states is X programming pulses. The non-volatile memory system limits the amount of programming for a second type of group of the non-volatile memory cells based on a second parameter such that a maximum number of programming pulses applied to the second type of group of non-volatile memory cells to program to the last data state after the second type of group of non-volatile memory cells completed programming to the other data states is Y programming pulses.

公开(公告)号：US12094546B2

公开(公告)日：2024-09-17

申请号：US17589789

申请日：2022-01-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yi Song ,  Jiahui Yuan ,  Yanjie Wang

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

Abstract: In order to decrease the width of threshold voltage distributions of programmed memory cells without unreasonably increasing the time needed to complete programming, a non-volatile memory uses a zone based program speed adjustment. The non-volatile memory starts programming a first set of the non-volatile memory cells until a minimum number of memory cells of the first set of non-volatile memory cells reach a first threshold voltage. In response to the minimum number of memory cells reaching the first threshold voltage, the first set of non-volatile memory cells are categorized into zones/groups based on threshold voltage. The speed of programming is then adjusted differently for each zone/group and programming is completed for the first set of non-volatile memory cells.

公开(公告)号：US12051468B2

公开(公告)日：2024-07-30

申请号：US17530196

申请日：2021-11-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jiahui Yuan ,  Deepanshu Dutta

IPC: G11C16/14 ,  G11C7/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/14 ,  G11C7/1048 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30

Abstract: Programming a plurality of non-volatile memory cells includes performing a soft erase process during the programming. The soft erase process includes pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging.

公开(公告)号：US20240203506A1

公开(公告)日：2024-06-20

申请号：US18357399

申请日：2023-07-24

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C5/06 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C5/063 ,  G11C16/3404

Abstract: A non-volatile memory system programs memory cells from an erased threshold voltage distribution to programmed threshold voltage distributions by performing hole pre-charging of channels of unselected NAND strings in a selected block of a selected plane including applying a source voltage to a selected signal line of a plurality of signal lines that are isolated from each other. The selected signal line is positioned between the selected block and an unselected block and is connected to a selected source line of a plurality of source lines that are isolated from each other. The selected source line is connected to the selected block. The source voltage is greater in magnitude than any predetermined threshold voltage of the erased threshold voltage distribution. After the pre-charging, the system boosts channels of unselected NAND strings in the selected block and applies a program voltage to selected NAND strings in the selected block.

公开(公告)号：US20240177788A1

公开(公告)日：2024-05-30

申请号：US18355339

申请日：2023-07-19

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Jiahui Yuan ,  Yanjie Wang

IPC: G11C16/34 ,  G11C16/14

CPC classification number: G11C16/3495 ,  G11C16/14 ,  G11C16/3445

Abstract: An apparatus is provided that includes a block of memory cells, and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a count of a number of times that the block of memory cells previously has been programmed and erased, determining an erase voltage based on the count, and applying an erase pulse having the erase voltage to the block of memory cells.

公开(公告)号：US11972805B2

公开(公告)日：2024-04-30

申请号：US17882273

申请日：2022-08-05

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Yanjie Wang ,  Jiahui Yuan

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3445

Abstract: In a non-volatile memory, to achieve a shallow and tight erased threshold voltage distribution, a process is performed that includes erasing a group of non-volatile memory cells, identifying a first set of the bit lines that are connected to non-volatile memory cells of the group that are erased past a lower limit for erased non-volatile memory cells and identifying a second set of the bit lines that are connected to non-volatile memory cells of the group that are not erased past the lower limit for erased non-volatile memory cells, and applying programming to non-volatile memory cells connected to the first set of bit lines while inhibiting programming for non-volatile memory cells connected to the second set of bit lines.

公开(公告)号：US20240136001A1

公开(公告)日：2024-04-25

申请号：US18357489

申请日：2023-07-23

Applicant: SanDisk Technologies LLC

Inventor： Abu Naser Zainuddin ,  Jiahui Yuan ,  Toru Miwa

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  H01L25/0657

Abstract: A memory system programs memory cells connected to a selected word line by applying doses of programming and performing program-verify between doses. An efficient and low current program-verify operation includes: while scanning the results of a previous program-verify operation, ramp up voltages on the select lines for the next program-verify operation without waiting for the scan to complete and ramp up voltages on unselected word lines for the next program-verify operation following a step signal (so that voltage applied to the unselected word lines rise in steps) without waiting for the scan to complete.

公开(公告)号：US20240127891A1

公开(公告)日：2024-04-18

申请号：US18356760

申请日：2023-07-21

Applicant: SanDisk Technologies LLC

Inventor： Abu Naser Zainuddin ,  Parth Amin ,  Xiaochen Zhu ,  Jiahui Yuan ,  Anubhav Khandelwal ,  Vishwanath Basavaegowda Shanthakumar

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3459 ,  H01L25/0657

Abstract: Technology is disclosed herein in which a duration of a program pulse used to program non-volatile memory cells such as NAND may be increased responsive to a programming failure using a shorter duration program pulse. The duration of at least one program pulse may be increased for at least one group of memory cells in response to a failure to program a group using a default program pulse duration. The group that experiences the increased duration program pulse may be the same group for which the program operation failed using the shorter program pulse or may be a different group than the group for which the program operation failed using the shorter program pulse.

公开(公告)号：US11961563B2

公开(公告)日：2024-04-16

申请号：US17825321

申请日：2022-05-26

Applicant: SanDisk Technologies LLC

Inventor： Towhidur Razzak ,  Jiahui Yuan ,  Deepanshu Dutta

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L25/065

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3459 ,  H01L25/0657 ,  H01L2225/06562

Abstract: Technology is disclosed herein for a memory system that balances peak Icc with programming speed. A memory system applies voltages to respective word lines during a verify operation that balances peak Icc with programming speed. The voltages for which the ramp rate is controlled include a read pass voltage applied to unselected word lines and a spike voltage applied to the selected word line at the beginning of the verify. The ramp rate of the voltages is slow enough to keep the peak Icc during verify to a target peak Icc regardless of which word line is selected for verify. However, the ramp rate of the voltages to the word lines during verify is fast enough to make use of the target peak Icc in order achieve faster programming. Therefore, the impact on programming time is minimized while staying within the allowed peak Icc.

公开(公告)号：US20240046996A1

公开(公告)日：2024-02-08

申请号：US17882273

申请日：2022-08-05

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Yanjie Wang ,  Jiahui Yuan

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3445

Abstract: In a non-volatile memory, to achieve a shallow and tight erased threshold voltage distribution, a process is performed that includes erasing a group of non-volatile memory cells, identifying a first set of the bit lines that are connected to non-volatile memory cells of the group that are erased past a lower limit for erased non-volatile memory cells and identifying a second set of the bit lines that are connected to non-volatile memory cells of the group that are not erased past the lower limit for erased non-volatile memory cells, and applying programming to non-volatile memory cells connected to the first set of bit lines while inhibiting programming for non-volatile memory cells connected to the second set of bit lines.