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公开(公告)号：US20240071527A1
公开(公告)日：2024-02-29
申请号：US17896330
申请日：2022-08-26
Applicant: SanDisk Technologies LLC
Inventor： Xiaoyu Che , Yanjie Wang , Runchen Fang
CPC classification number: G11C16/3459 , G11C16/08 , G11C16/3495
Abstract: A storage device comprises: a non-volatile memory including control circuitry and an array of memory cells formed using a set of word lines and a set of bit lines. A controller, coupled to the non-volatile memory, configured to: determine, based on a stage of a product lifetime of the non-volatile memory, a negative word line setting for implementing during performance of a first operation; perform the first operation, the first operation including adjusting, based on the negative word line setting, a negative word line relative parameter; determine, based on another stage of the product lifetime of the non-volatile memory, another negative word line setting for implementing during performance of a second operation; and perform the second operation, the second operation including adjusting, based on the other negative word line setting, another negative word line relative parameter.
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公开(公告)号：US20230395157A1
公开(公告)日：2023-12-07
申请号：US17832441
申请日：2022-06-03
Applicant: SanDisk Technologies LLC
Inventor： Yi Song , Jiahui Yuan , Yanjie Wang
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/10
Abstract: In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.
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3.发明公开公开(公告)号：US20230317174A1
公开(公告)日：2023-10-05
申请号：US17706993
申请日：2022-03-29
Applicant: SanDisk Technologies LLC
Inventor： Yanjie Wang , Guirong Liang , Xiaoyu Che , Yi Song
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/32 , G11C11/5642
Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings coupled to one of a plurality of bit lines and are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to read each of the memory cells in a read operation. For each one of the memory cells, the control means is also configured to offset at least one of a bit line settling time and a kick voltage during the read operation based on a probability of at least one neighboring one of the plurality of bit lines being coupled to the memory cells retaining the threshold voltage corresponding to a different one of the plurality of data states than the one of the memory cells.
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公开(公告)号：US20220208276A1
公开(公告)日：2022-06-30
申请号：US17135071
申请日：2020-12-28
Applicant: SanDisk Technologies LLC
Inventor： Jianzhi Wu , Jia Li , Yanjie Wang
Abstract: A memory apparatus and method of operation are provided. The apparatus includes a page of memory cells connected to a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and strings and identifies the memory cells having the threshold voltage less than a primary demarcation threshold voltage of a series for demarcating between memory states in a page read. The control circuit also identifies the memory cells having the threshold voltage less than a secondary demarcation threshold voltage of the series. The control circuit supplies a near zero voltage to the strings of the memory cells identified as having the threshold voltages less than at least one of the primary and secondary demarcation threshold voltages to inhibit conduction currents while identifying the memory cells having the threshold voltage less than a tertiary demarcation threshold voltage.
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公开(公告)号：US12094546B2
公开(公告)日：2024-09-17
申请号：US17589789
申请日：2022-01-31
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Yi Song , Jiahui Yuan , Yanjie Wang
CPC classification number: G11C16/3459 , G11C16/102 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/3404
Abstract: In order to decrease the width of threshold voltage distributions of programmed memory cells without unreasonably increasing the time needed to complete programming, a non-volatile memory uses a zone based program speed adjustment. The non-volatile memory starts programming a first set of the non-volatile memory cells until a minimum number of memory cells of the first set of non-volatile memory cells reach a first threshold voltage. In response to the minimum number of memory cells reaching the first threshold voltage, the first set of non-volatile memory cells are categorized into zones/groups based on threshold voltage. The speed of programming is then adjusted differently for each zone/group and programming is completed for the first set of non-volatile memory cells.
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Patent Agency Ranking
公开(公告)号：US20240177788A1
公开(公告)日：2024-05-30
申请号：US18355339
申请日：2023-07-19
Applicant: SanDisk Technologies LLC
Inventor： Yi Song , Jiahui Yuan , Yanjie Wang
CPC classification number: G11C16/3495 , G11C16/14 , G11C16/3445
Abstract: An apparatus is provided that includes a block of memory cells, and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a count of a number of times that the block of memory cells previously has been programmed and erased, determining an erase voltage based on the count, and applying an erase pulse having the erase voltage to the block of memory cells.
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公开(公告)号：US11972805B2
公开(公告)日：2024-04-30
申请号：US17882273
申请日：2022-08-05
Applicant: SanDisk Technologies LLC
Inventor： Yi Song , Yanjie Wang , Jiahui Yuan
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/10 , G11C16/3445
Abstract: In a non-volatile memory, to achieve a shallow and tight erased threshold voltage distribution, a process is performed that includes erasing a group of non-volatile memory cells, identifying a first set of the bit lines that are connected to non-volatile memory cells of the group that are erased past a lower limit for erased non-volatile memory cells and identifying a second set of the bit lines that are connected to non-volatile memory cells of the group that are not erased past the lower limit for erased non-volatile memory cells, and applying programming to non-volatile memory cells connected to the first set of bit lines while inhibiting programming for non-volatile memory cells connected to the second set of bit lines.
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公开(公告)号：US20240046996A1
公开(公告)日：2024-02-08
申请号：US17882273
申请日：2022-08-05
Applicant: SanDisk Technologies LLC
Inventor： Yi Song , Yanjie Wang , Jiahui Yuan
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/10 , G11C16/3445
Abstract: In a non-volatile memory, to achieve a shallow and tight erased threshold voltage distribution, a process is performed that includes erasing a group of non-volatile memory cells, identifying a first set of the bit lines that are connected to non-volatile memory cells of the group that are erased past a lower limit for erased non-volatile memory cells and identifying a second set of the bit lines that are connected to non-volatile memory cells of the group that are not erased past the lower limit for erased non-volatile memory cells, and applying programming to non-volatile memory cells connected to the first set of bit lines while inhibiting programming for non-volatile memory cells connected to the second set of bit lines.
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公开(公告)号：US20230326531A1
公开(公告)日：2023-10-12
申请号：US17718124
申请日：2022-04-11
Applicant: SanDisk Technologies LLC
Inventor： Yanjie Wang , Ohwon Kwon , Kou Tei , Tai-Yuan Tseng , Yasue Yamamoto , Yonggang Wu , Guirong Liang
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/24 , G11C16/08 , G11C16/16 , G11C16/30 , G11C16/3459 , H01L25/0657
Abstract: Technology is disclosed herein for a memory system having a dynamic supply voltage to sense amplifiers. In an aspect, the supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.
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10.发明授权公开(公告)号：US11636897B2
公开(公告)日：2023-04-25
申请号：US17191153
申请日：2021-03-03
Applicant: SanDisk Technologies LLC
Inventor： Yanjie Wang , Henry Chin , Guirong Liang , Jianzhi Wu
Abstract: An apparatus includes a plurality of solid-state storage elements, a plurality of control lines coupled to the plurality of solid-state storage elements, and control circuitry in communication with the plurality of control lines. The control circuitry is configured to during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a predicted parasitic capacitance associated with the programming state of the control lines, and during a second phase of the control line pre-charging stage, charge the one or more unselected bit lines to an inhibit voltage level using an unregulated charging current.
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