公开(公告)号：US20240302432A1

公开(公告)日：2024-09-12

申请号：US18597499

申请日：2024-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hobin SONG ,  Juyun Lee ,  Jiyoung Kim ,  Jaehyun Park ,  Sooeun Lee ,  Insik Hwang

IPC: G01R31/3183 ,  G01R31/317 ,  G01R31/3187 ,  H03K5/00 ,  H03K5/13 ,  H03L7/08 ,  H03L7/081

CPC classification number: G01R31/318328 ,  G01R31/31724 ,  G01R31/3187 ,  H03K5/13 ,  H03L7/0807 ,  H03K2005/00052 ,  H03L7/0812

Abstract: A system-on-chip includes a clock generation circuit configured to generate a reference clock of a first phase; a transmission circuit comprising a serializer configured to serialize data according to the reference clock of the first phase; a reception circuit comprising a clock data recovery (CDR) circuit configured to receive the serialized data and generate a first recovery clock and recovery data; and a Built In Self Test (BIST) circuit including a CDR performance monitoring circuit configured to generate a control signal provided to a delay controller configured to delay a clock signal by a preset phase difference, and the delay controller configured to delay the clock signal in response to the control signal by the preset phase difference and provide the delayed clock signal to the transmission circuit.

公开(公告)号：US11940847B2

公开(公告)日：2024-03-26

申请号：US18295496

申请日：2023-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jonggeun Yoon ,  Jebin Lee ,  Pilwon Seo ,  Jiyoung Kim ,  Jiwoo Lee

IPC: G06F1/16 ,  G06F3/02 ,  G06F3/0346 ,  G06F3/0354 ,  G06F3/038 ,  G09G3/00

CPC classification number: G06F1/1652 ,  G06F1/1624 ,  G06F1/1677 ,  G06F3/02 ,  G06F3/0346 ,  G06F3/03545 ,  G06F3/038 ,  G09G3/035 ,  G09G2354/00

Abstract: This electronic device may comprise: a flexible display; a first rolling actuator configured to extend the flexible display in a first direction; a second rolling actuator configured to extend the flexible display in a second direction opposite to the first direction; and at least one processor. The at least one processor may be configured to: determine the mounting state of the electronic device; acquire information about the position of a peripheral device, which is linked with the electronic device, based on the mounting state satisfying a designated condition; set the extension direction of the flexible display on the basis of the information about the position of the peripheral device; and control the first rolling actuator and/or the second rolling actuator to extend the flexible display in the first direction and/or the second direction on the basis of the set extension direction.

公开(公告)号：US20230422523A1

公开(公告)日：2023-12-28

申请号：US18180366

申请日：2023-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Dohyung Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B80/00 ,  H10B43/27

CPC classification number: H10B80/00 ,  H10B43/27

Abstract: A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure on the first substrate, and a cell array structure on the peripheral circuit structure. The cell array structure includes a stacked structure including gate electrodes extending in a first direction, a source structure on the stacked structure, and a second substrate in contact with the source structure. The source structure includes a first source conductive pattern between the second substrate and the stacked structure and a second source conductive pattern on the first source conductive pattern. The second source conductive pattern includes a first source part between the first source conductive pattern and the second substrate, a source connection part passing through the second substrate and extending in the first direction, and a second source part on the second substrate and connected to the first source part through the source connection part.

公开(公告)号：US11837545B2

公开(公告)日：2023-12-05

申请号：US17399043

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungwoo Song ,  Ye-Ro Lee ,  Kwangtae Hwang ,  Kwangmin Kim ,  Yong Kwan Kim ,  Jiyoung Kim

IPC: H10B12/00 ,  H01L23/532 ,  H01L27/02 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5329 ,  H01L21/768 ,  H01L27/0207 ,  H10B12/033 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/5222

Abstract: A semiconductor device including a substrate includes an active region. A bit line structure extends across the active region. A landing pad is disposed on an end portion of the active region. A first spacer is disposed between the bit line structure and the landing pad. A second spacer is disposed between the first spacer and the landing pad. An air spacer is disposed between the first spacer and the second spacer. A capping pattern is disposed between a sidewall of the landing pad and a sidewall of the bit line structure. The capping pattern defines a top surface of the air spacer and comprises a metallic material.

公开(公告)号：US11817405B2

公开(公告)日：2023-11-14

申请号：US17496488

申请日：2021-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sumin Ahn ,  Byungjun Kang ,  Jiyoung Kim ,  Hae Seok Park ,  Chulsoon Chang

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/02 ,  H01L21/481 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0221 ,  H01L2224/02206 ,  H01L2224/02215 ,  H01L2224/02311 ,  H01L2224/05548 ,  H01L2224/13024 ,  H01L2224/16227

Abstract: Disclosed are semiconductor devices and their fabricating methods. The semiconductor device comprises a dielectric layer, a trench formed in the dielectric layer, a metal pattern that conformally covers a top surface of the dielectric layer, an inner side surface of the trench, and a bottom surface of the trench, a first protection layer that conformally covers the metal pattern, and a second protection layer that covers the first protection layer. A cavity is formed in the trench. The cavity is surrounded by the first protection layer. The first protection layer has an opening that penetrates the first protection layer and extends from a top surface of the first protection layer. The opening is connected to the cavity. A portion of the second protection layer extends into the opening and closes the cavity.

公开(公告)号：US20230142328A1

公开(公告)日：2023-05-11

申请号：US18093030

申请日：2023-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minho Kim ,  Hakseung Han ,  Jiyoung Kim ,  Jinback Park

IPC: G06T7/00 ,  G02B27/14 ,  G01N21/95

CPC classification number: G06T7/0006 ,  G02B27/14 ,  G01N21/9501 ,  G06T2207/30148

Abstract: An apparatus and method of measuring pattern uniformity, and a method of manufacturing a mask by using the measurement method are provided. The measurement apparatus includes a light source configured to generate and output light, a stage configured to support a measurement target, an optical system configured to transfer the light, output from the light source, to the measurement target supported on the stage, and a first detector configured to detect light reflected and diffracted by the measurement target, or diffracted by passing through the measurement target, wherein the first detector is configured to detect a pupil image of a pupil plane and to measure pattern uniformity of an array area of the measurement target on the basis of intensity of at least one of zero-order light and 1st-order light of the pupil image.

公开(公告)号：US11626411B2

公开(公告)日：2023-04-11

申请号：US17137684

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Daewon Kim ,  Dongjin Lee

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4097

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device may include a first substrate comprising a cell array region, a first interlayer insulating layer covering the first substrate, a second substrate disposed on the first interlayer insulating layer, the second substrate including a core region electrically connected to the cell array region, a first adhesive insulating layer interposed between the first interlayer insulating layer and the second substrate, and contact plugs penetrating the second substrate, the first adhesive insulating layer, and the first interlayer insulating layer and electrically connecting the cell array region with the core region.

公开(公告)号：US11616065B2

公开(公告)日：2023-03-28

申请号：US17090419

申请日：2020-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Kiseok Lee ,  Bong-Soo Kim ,  Junsoo Kim ,  Dongsoo Woo ,  Kyupil Lee ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/06 ,  H01L49/02

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a substrate. The semiconductor memory device includes a plurality of memory cell transistors vertically stacked on the substrate. The semiconductor memory device includes a first conductive line connected to a source region of at least one of the plurality of memory cell transistors. The semiconductor memory device includes a second conductive line connected to a plurality of gate electrodes of the plurality of memory cell transistors. Moreover, the semiconductor memory device includes a data storage element connected to a drain region of the at least one of the plurality of memory cell transistors.

公开(公告)号：US20230084497A1

公开(公告)日：2023-03-16

申请号：US17828170

申请日：2022-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Moorym Choi ,  Junyoung Choi ,  Jungtae Sung ,  Sanghee Yoon ,  Wooyong Jeon

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: A peripheral circuit structure may be formed on a first surface of a first substrate. A cell array structure may be formed on a first surface of a second substrate and may be attached to the peripheral circuit structure such that those first surfaces face each other. The cell array structure may be formed by forming a back-side via and a preliminary contact pad on the second substrate and forming a semiconductor layer. A hole may be formed to penetrate the semiconductor layer and to expose the preliminary contact pad and may be formed by removing an upper portion of the preliminary contact pad, thereby forming a contact pad separated from the semiconductor layer. The method may further include forming a stack on the semiconductor layer, an insulating layer on the stack, and a contact plug penetrating the insulating layer and connected to the contact pad.

公开(公告)号：US11600609B2

公开(公告)日：2023-03-07

申请号：US17204394

申请日：2021-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungtae Sung ,  Junyoung Choi ,  Jiyoung Kim ,  Yoonjo Hwang

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L25/00 ,  H01L25/065

Abstract: Disclosed are three-dimensional semiconductor memory devices and electronic systems including the same. The three-dimensional semiconductor memory device comprises a first structure and a second structure in contact with the first structure. Each of the first and second structures includes a substrate, a peripheral circuit region on the substrate, and a cell array region including a stack structure on the peripheral circuit region, a plurality of vertical structures that penetrate the stack structure, and a common source region in contact with the vertical structures. The stack structure is between the peripheral circuit region and the common source region. The common source regions of the first and second structures are connected with each other.