公开(公告)号：US20180367164A1

公开(公告)日：2018-12-20

申请号：US15793870

申请日：2017-10-25

Applicant: Seagate Technology LLC

Inventor： Marcus Marrow ,  Jason Bellorado ,  Vincent Brendan Ashe ,  Rishi Ahuja

IPC: H03M13/41 ,  H03M1/00 ,  H04B1/7105 ,  H03M13/29

Abstract: An apparatus may include a circuit configured to process an input signal using a set of channel parameters. The circuit may produce, using a first adaptation algorithm, a first set of channel parameters for use by the circuit as the set of channel parameters in processing the input signal. The circuit may further approximate a second set of channel parameters of a second adaptation algorithm for use by the circuit as the set of channel parameters in processing the input signal based on the first set of channel parameters and a relationship between a third set of channel parameters generated using the first adaptation algorithm and a fourth set of channel parameters generated using the second adaptation algorithm. In addition, the circuit may perform the processing of the input signal using the second set of channel parameters as the set of channel parameters.

公开(公告)号：US20180366156A1

公开(公告)日：2018-12-20

申请号：US15722641

申请日：2017-10-02

Applicant: Seagate Technology LLC

Inventor： Marcus Marrow ,  Jason Bellorado ,  Zheng Wu

IPC: G11B20/10

Abstract: Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.

公开(公告)号：US09928854B1

公开(公告)日：2018-03-27

申请号：US15586217

申请日：2017-05-03

Applicant: Seagate Technology LLC

Inventor： Jason Charles Jury ,  Marcus Marrow ,  Michael J Link ,  Jason Bellorado

IPC: G11B20/10 ,  G11B5/035 ,  G11B5/012 ,  G06F11/07 ,  G11B21/10 ,  G11B5/00

CPC classification number: G11B5/012 ,  G06F11/0793 ,  G11B5/035 ,  G11B5/09 ,  G11B21/106 ,  G11B2005/0013

Abstract: An apparatus may include a circuit configured to generate a set of first ADC samples based on a first signal associated with a first read head position and a failed segment and to generate a set of second ADC samples based on a second signal associated with a second read head position and the failed segment. The circuit may then generate, by a MISO equalizer, a set of equalized ADC samples based on the set of first ADC samples and the set of second ADC samples.