公开(公告)号：US10255931B1

公开(公告)日：2019-04-09

申请号：US15912480

申请日：2018-03-05

Applicant: Seagate Technology LLC

Inventor： Jason Charles Jury ,  Marcus Marrow ,  Michael J Link ,  Jason Bellorado

IPC: G11B20/10 ,  G11B5/035 ,  G11B5/012 ,  G11B21/10 ,  G06F11/07 ,  G11B5/00

Abstract: An apparatus may include a circuit configured to generate a set of first ADC samples based on a first signal associated with a first read head position and a failed segment and to generate a set of second ADC samples based on a second signal associated with a second read head position and the failed segment. The circuit may then generate, by a MISO equalizer, a set of equalized ADC samples based on the set of first ADC samples and the set of second ADC samples.

公开(公告)号：US09928854B1

公开(公告)日：2018-03-27

申请号：US15586217

申请日：2017-05-03

Applicant: Seagate Technology LLC

Inventor： Jason Charles Jury ,  Marcus Marrow ,  Michael J Link ,  Jason Bellorado

IPC: G11B20/10 ,  G11B5/035 ,  G11B5/012 ,  G06F11/07 ,  G11B21/10 ,  G11B5/00

CPC classification number: G11B5/012 ,  G06F11/0793 ,  G11B5/035 ,  G11B5/09 ,  G11B21/106 ,  G11B2005/0013

Abstract: An apparatus may include a circuit configured to generate a set of first ADC samples based on a first signal associated with a first read head position and a failed segment and to generate a set of second ADC samples based on a second signal associated with a second read head position and the failed segment. The circuit may then generate, by a MISO equalizer, a set of equalized ADC samples based on the set of first ADC samples and the set of second ADC samples.