公开(公告)号：US08295071B2

公开(公告)日：2012-10-23

申请号：US13233580

申请日：2011-09-15

Applicant: Terry R. Lee ,  Kevin J. Ryan

Inventor： Terry R. Lee ,  Kevin J. Ryan

IPC: G11C5/06

CPC classification number: G11C7/1054 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1081

Abstract: Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module.

Abstract translation: 公开了光耦合存储器系统。 在一个实施例中，系统存储器包括载体衬底和附接到载体衬底并可操作以发射和接收光信号的控制器以及第一和第二存储器模块。 第一存储器模块的模块衬底具有形成在其中的孔，该孔可操作以为控制器和第二存储器模块的光发射器/接收器单元之间的光信号提供光路。

公开(公告)号：US08171181B2

公开(公告)日：2012-05-01

申请号：US12115047

申请日：2008-05-05

Applicant: Terry R. Lee ,  David Ovard ,  Roy Greeff ,  Robert N. Leibowitz ,  Victor Tsai

Inventor： Terry R. Lee ,  David Ovard ,  Roy Greeff ,  Robert N. Leibowitz ,  Victor Tsai

IPC: G06F13/14

CPC classification number: G11C7/1045 ,  G11C5/00

Abstract: A memory module has one or more memory devices, a controller in communication with the one or more memory devices, and a plurality of input/output ports. The controller is configured to configure each input/output port as an input, an output, or a bidirectional input/output.

Abstract translation: 存储器模块具有一个或多个存储器设备，与一个或多个存储器设备通信的控制器以及多个输入/输出端口。 控制器配置为将每个输入/输出端口配置为输入，输出或双向输入/输出。

公开(公告)号：US08127081B2

公开(公告)日：2012-02-28

申请号：US12185615

申请日：2008-08-04

Applicant: Terry R. Lee ,  Joseph Jeddeloh

Inventor： Terry R. Lee ,  Joseph Jeddeloh

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6022 ,  G06F2212/6024 ,  G06F2212/6026

Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.

Abstract translation: 存储器模块包括耦合到多个存储器件的存储器集线器。 存储器集线器包括历史逻辑，该历史逻辑基于读取存储器请求来预测存储器设备中哪个地址可能随后被读取的日期。 历史逻辑将对应于预测地址的预取建议应用于存储器定序器，其使用预取建议来生成耦合到存储器设备的预取请求。 响应于预取建议从存储器件读取的数据被存储在预取缓冲器中。 标签逻辑存储与预取数据的地址对应的预取地址。 标签逻辑将存储器请求地址与预取地址进行比较，以确定所请求的读取数据是否存储在预取缓冲器中。 如果是，则从预取缓冲器读取所请求的数据。 否则，从存储器件读取所请求的数据。

公开(公告)号：US08106520B2

公开(公告)日：2012-01-31

申请号：US12209052

申请日：2008-09-11

Applicant: Brent Keeth ,  Mark Hiatt ,  Terry R. Lee ,  Mark Tuttle ,  Rahul Advani ,  John F. Schreck

Inventor： Brent Keeth ,  Mark Hiatt ,  Terry R. Lee ,  Mark Tuttle ,  Rahul Advani ,  John F. Schreck

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01004 ,  H01L2924/15311 ,  Y10T29/49165

Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.

Abstract translation: 一些实施例包括装置，系统和方法，其具有底座，第一管芯，第二管芯，第二管芯和第二管芯，第二管芯和第二管芯和第二管芯，第二管芯和第二管芯， 被配置为在所述基座与所述第一和第二骰子中的至少一个之间传送信号。

公开(公告)号：US20100191924A1

公开(公告)日：2010-07-29

申请号：US12754011

申请日：2010-04-05

Applicant: Joseph M. Jeddeloh ,  Terry R. Lee

Inventor： Joseph M. Jeddeloh ,  Terry R. Lee

IPC: G06F12/00

CPC classification number: G06F13/1642 ,  G06F13/1673

Abstract: A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

Abstract translation: 计算机系统包括耦合到多个存储器模块的存储器集线器控制器。 存储器集线器控制器包括将存储器请求和对应的请求标识符耦合到存储器模块的存储器请求队列。 每个存储器模块基于存储器请求访问存储器件，并且当对应的存储器请求被服务时，从请求标识符产生响应状态信号。 这些响应状态信号与存储器模块耦合到存储器集线器控制器，或者与任何读取数据分离。 存储器集线器控制器使用响应状态信号来控制对存储器模块的存储器请求的耦合，从而控制每个存储器模块中未完成的存储器请求的数量。

公开(公告)号：US07529896B2

公开(公告)日：2009-05-05

申请号：US11433201

申请日：2006-05-11

Applicant: Joseph M. Jeddeloh ,  Terry R. Lee

Inventor： Joseph M. Jeddeloh ,  Terry R. Lee

IPC: G06F13/00 ,  G06F3/00

CPC classification number: G11C7/1006 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4093 ,  G11C11/4096

Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first be coupled to the memory devices. The write request addresses are also posted in the buffer and compared to subsequent read request addresses. In the event of a positive comparison indicating that a read request is directed to an address to which an earlier write request was directed, the read data are provided from the buffer. When the memory devices are not busy servicing read request, the write requests can be transferred from the posted write buffer to the memory devices. The write requests may also be accumulated in the posted write buffer until either a predetermined number of write requests have been accumulated or the write requests have been posted for a predetermined duration.

Abstract translation: 存储器模块包括耦合到多个存储器件的存储器集线器。 存储器集线器包括存储写入请求的已发布的写入缓冲器，以便随后发出的读取请求可以首先耦合到存储器件。 写请求地址也被发布在缓冲区中，并与随后的读请求地址进行比较。 在正面比较的情况下，指示读请求被引导到较早写请求所针对的地址，从缓冲器提供读数据。 当存储器件不忙于读取请求时，写入请求可以从发布的写入缓冲区传送到存储器件。 写入请求也可以被累积在发布的写入缓冲器中，直到预定数量的写入请求已经被累积或写入请求已经被发布了预定的持续时间。

公开(公告)号：US20080301533A1

公开(公告)日：2008-12-04

申请号：US11639950

申请日：2006-12-15

Applicant: Terry R. Lee ,  Joseph M. Jeddeloh

Inventor： Terry R. Lee ,  Joseph M. Jeddeloh

IPC: H03M13/00

CPC classification number: H04B10/2504 ,  H04L1/0001 ,  H04L1/242 ,  H04L7/043

Abstract: A method and system that dynamically adjusts link control parameters of a communications network. The communications network includes a transmitter coupled through a first data link to a receiver. The transmitter and receiver each have at least one associated link control parameter that affects the operation of that component. According to one method, data signals are transmitted over the first data link and the transmitted data signals are captured. The values of the captured data signals are compared to expected values for those signals, and the values of the link control parameters are adjusted to successfully capture the transmitted digital signals.

Abstract translation: 一种动态调整通信网络链路控制参数的方法和系统。 通信网络包括通过第一数据链路耦合到接收机的发射机。 发射器和接收器各自具有影响该部件的操作的至少一个相关联的链接控制参数。 根据一种方法，通过第一数据链路传输数据信号，并且捕获发送的数据信号。 将捕获的数据信号的值与这些信号的期望值进行比较，并且调整链路控制参数的值以成功捕获所发送的数字信号。

公开(公告)号：US07412566B2

公开(公告)日：2008-08-12

申请号：US11510150

申请日：2006-08-24

Applicant: Terry R. Lee ,  Joseph M. Jeddeloh

Inventor： Terry R. Lee ,  Joseph M. Jeddeloh

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6022 ,  G06F2212/6024 ,  G06F2212/6026

Abstract: A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.

Abstract translation: 存储器模块包括耦合到多个存储器件的存储器集线器。 存储器集线器包括历史逻辑，其基于读取存储器请求来预测存储器件中的哪些地址可能随后从其读取数据。 历史逻辑将对应于预测地址的预取建议应用于存储器定序器，其使用预取建议来生成耦合到存储器设备的预取请求。 响应于预取建议从存储器件读取的数据被存储在预取缓冲器中。 标签逻辑存储与预取数据的地址对应的预取地址。 标签逻辑将存储器请求地址与预取地址进行比较，以确定所请求的读取数据是否存储在预取缓冲器中。 如果是，则从预取缓冲器读取所请求的数据。 否则，从存储器件读取所请求的数据。

公开(公告)号：US07227261B2

公开(公告)日：2007-06-05

申请号：US10648164

申请日：2003-08-26

Applicant: Larry D. Kinsman ,  Jerry M. Brooks ,  Warren M. Farnworth ,  Walter L. Moden ,  Terry R. Lee

Inventor： Larry D. Kinsman ,  Jerry M. Brooks ,  Warren M. Farnworth ,  Walter L. Moden ,  Terry R. Lee

IPC: H01L23/34

CPC classification number: H05K3/301 ,  H01L2924/0002 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. At least a portion of the semiconductor device may be exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. The alignment device may secure the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.

Abstract translation: 一种可垂直安装的半导体器件组件，包括半导体器件和用于将半导体器件附着到载体衬底的机构。 半导体器件的每个接合焊盘都设置在其单个边缘附近。 可以暴露半导体器件的至少一部分。 对准装置附接到载体基板。 可垂直安装的半导体器件封装上的安装元件与对准装置接合以使半导体器件和对准器件互连。 对准装置可以使垂直安装的半导体器件封装相对于载体衬底垂直地固定。 接合焊盘和载体基板上的对应端子之间的距离非常小以减少阻抗。 垂直安装的半导体器件封装也可以容易地用户升级。

公开(公告)号：US07076697B2

公开(公告)日：2006-07-11

申请号：US10667388

申请日：2003-09-23

Applicant: Terry R. Lee

Inventor： Terry R. Lee

IPC: G06F11/00

CPC classification number: G11C29/50012 ,  G06F11/24 ,  G11C11/401 ,  G11C29/50 ,  G11C2207/2254

Abstract: A method and apparatus for monitoring the response times of computer system components in order to improve computer system reliability and performance are provided. The method and apparatus are particularly applicable to computer systems with memory circuits, such as SLDRAMs, that have programmable response times. A response time monitoring circuit in the form of a phase detector includes a plurality of flip-flops with the data inputs commonly connected to receive a response ready signal from a component, such as a memory circuit, in response to a command to perform a task. Each clock input of the flip-flop is connected to a clock signal at a different phase of a response period. The outputs of the flip-flops determine the phase at which the response ready signal was generated by the component.