公开(公告)号：US08324100B2

公开(公告)日：2012-12-04

申请号：US13029950

申请日：2011-02-17

Applicant: Salman Akram ,  William Mark Hiatt ,  Steven Oliver ,  Alan G. Wood ,  Sidney B. Rigg ,  James M. Wark ,  Kyle K. Kirby

Inventor： Salman Akram ,  William Mark Hiatt ,  Steven Oliver ,  Alan G. Wood ,  Sidney B. Rigg ,  James M. Wark ,  Kyle K. Kirby

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2924/09701

Abstract: Methods of forming a conductive via may include forming a blind via hole partially through a substrate, forming an aluminum film on surfaces of the substrate, removing a first portion of the aluminum film from some surfaces, selectively depositing conductive material onto a second portion of the aluminum film, and exposing the blind via hole through a back side of the substrate. Methods of fabricating a conductive via may include forming at least one via hole through at least one unplated bond pad, forming a first adhesive over at least one surface of the at least one via hole, forming a dielectric over the first adhesive, forming a base layer over the dielectric and the at least one unplated bond pad, and plating nickel onto the base layer.

Abstract translation: 形成导电通孔的方法可以包括部分地穿过衬底形成盲孔，在衬底的表面上形成铝膜，从一些表面去除铝膜的第一部分，将导电材料选择性地沉积到第二部分上 铝膜，并且通过基板的背面露出盲孔。 制造导电通孔的方法可以包括通过至少一个未镀覆的焊盘形成至少一个通孔，在至少一个通孔的至少一个表面上形成第一粘合剂，在第一粘合剂上形成电介质，形成基底 层叠在电介质和至少一个未镀覆的焊盘上，并将镍镀在基底层上。

公开(公告)号：US08294273B2

公开(公告)日：2012-10-23

申请号：US12985570

申请日：2011-01-06

Applicant: Salman Akram ,  William Mark Hiatt ,  Steve Oliver ,  Alan G. Wood ,  Sidney B. Rigg ,  James M. Wark ,  Kyle K. Kirby

Inventor： Salman Akram ,  William Mark Hiatt ,  Steve Oliver ,  Alan G. Wood ,  Sidney B. Rigg ,  James M. Wark ,  Kyle K. Kirby

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/17181 ,  H01L2924/09701

Abstract: Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.

Abstract translation: 用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。 通孔可以形成有单个掩模，其中在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其它特征用作硬掩模。 通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。 可以在每个通孔的表面上形成阻挡层。 可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。 还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

公开(公告)号：US07504615B2

公开(公告)日：2009-03-17

申请号：US11727545

申请日：2007-03-27

Applicant: Warren M. Farnworth ,  Sidney B. Rigg ,  William Mark Hiatt ,  Alan G. Wood ,  Peter A. Benson ,  James M. Wark ,  David R. Hembree ,  Kyle K. Kirby ,  Charles M. Watkins ,  Salman Akram

Inventor： Warren M. Farnworth ,  Sidney B. Rigg ,  William Mark Hiatt ,  Alan G. Wood ,  Peter A. Benson ,  James M. Wark ,  David R. Hembree ,  Kyle K. Kirby ,  Charles M. Watkins ,  Salman Akram

IPC: H01L27/00 ,  H01L31/0232

CPC classification number: H01L27/00 ,  B33Y80/00 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14683 ,  H01L27/14687 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/00014

Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.

Abstract translation: 微电子成像器组件包括包括衬底的工件和在衬底上和/或衬底中的多个成像管芯。 基板包括前侧和后侧，并且成像管芯包括在基板的前侧的成像传感器和可操作地耦合到图像传感器的外部触点。 微电子成像器组件还包括相对于成像管芯叠加的光学支架。 光学支撑件可以直接在基板上或衬底上的盖上。 单个光学支撑件可以具有（a）与图像传感器中的一个对准的开口，以及（b）与图像传感器相距一定距离处的轴承元件。 微电子成像器组件还可以包括由光学器件支撑件安装或以其它方式承载的光学器件。

公开(公告)号：US06673649B1

公开(公告)日：2004-01-06

申请号：US10190019

申请日：2002-07-05

Applicant: William Mark Hiatt ,  Warren Farnworth

Inventor： William Mark Hiatt ,  Warren Farnworth

IPC: H01L2100

CPC classification number: H01L23/3114 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/467 ,  H01L23/473 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/10126 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A microelectronic package and method for forming such a package. In one embodiment, the package can include a microelectronic substrate having first connection sites, and a support member having second connection sites and third connection sites, with the third connection sites accessible for electrical coupling to other electrical structures. A plurality of electrically conductive couplers are connected between the first connection sites and the second connection sites, with neighboring conductive couplers being spaced apart to define at least one flow channel. The at least one flow channel is in fluid communication with a region external to the microelectronic substrate. The generally non-conductive material can be spaced apart from the support member to allow the microelectronic substrate to be separated from the support member.

公开(公告)号：US06426698B1

公开(公告)日：2002-07-30

申请号：US09573949

申请日：2000-05-19

Applicant: Larry Edward Frisa ,  Clinton Haris ,  Mark Hiatt

Inventor： Larry Edward Frisa ,  Clinton Haris ,  Mark Hiatt

IPC: G08B108

CPC classification number: G08B21/0216 ,  G08B13/1427 ,  G08B21/0227

Abstract: An apparatus related to a lot signalling device used to find misplaced lots. A remote control signalling device comprises a receiver section (5) for receiving an RF-command including a unique address of at least one of said plurality of remote control signalling devices (3) from a central control unit (1), an address memory (6) for storing the address of said remote control signalling device, an output section (7) for signalling an alarm upon receiving the RF-command, if said address included in the RF-command matches the stored address in said address memory (6). A method for processing items at different process stages comprises the steps of: transmitting RF-commands including a unique address of at least one of said plurality of remote control signalling devices by a central control unit (1), signalling an alarm by said remote control signalling device (3) upon reception of an RF-command from said central control unit (1).

Abstract translation: 与用于发现错位的批次信号装置相关的装置。 遥控信令装置包括接收机部分（5），用于从中央控制单元（1）接收包括所述多个远程控制信令装置（3）中的至少一个的唯一地址的RF命令，地址存储器 6），用于存储所述遥控信令装置的地址;如果包括在所述RF指令中的所述地址与所述地址存储器（6）中存储的地址匹配，则用于在接收到所述RF命令时用于发出警报的输出部分（7） 。 一种用于在不同处理阶段处理物品的方法包括以下步骤：通过中央控制单元（1）发送包括至少一个所述多个远程控制信令装置的唯一地址的RF指令，通过所述遥控器 信令装置（3）在从所述中央控制单元（1）接收到RF命令时。

公开(公告)号：US08531046B2

公开(公告)日：2013-09-10

申请号：US13099672

申请日：2011-05-03

Applicant: Dave Pratt ,  Kyle K. Kirby ,  Steve Oliver ,  Mark Hiatt

Inventor： Dave Pratt ,  Kyle K. Kirby ,  Steve Oliver ,  Mark Hiatt

IPC: H01L23/544

CPC classification number: H01L21/682 ,  H01L21/67259 ,  H01L21/76898 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: The invention includes methods of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit, methods of positioning a semiconductor substrate comprising an integrated circuit, methods of processing a semiconductor substrate, and semiconductor devices. In one implementation, a method of determining x-y spatial orientation of a semiconductor substrate comprising an integrated circuit includes providing a semiconductor substrate comprising at least one integrated circuit die. The semiconductor substrate comprises a circuit side, a backside, and a plurality of conductive vias extending from the circuit side to the backside. The plurality of conductive vias on the semiconductor substrate backside is examined to determine location of portions of at least two of the plurality of conductive vias on the semiconductor substrate backside. From the determined location, x-y spatial orientation of the semiconductor substrate is determined. Other aspects and implementations are contemplated.

Abstract translation: 本发明包括确定包括集成电路的半导体衬底的x-y空间取向的方法，包括集成电路的半导体衬底的定位方法，半导体衬底的处理方法以及半导体器件。 在一个实现中，确定包括集成电路的半导体衬底的x-y空间取向的方法包括提供包括至少一个集成电路管芯的半导体衬底。 半导体衬底包括电路侧，背面以及从电路侧延伸到背面的多个导电通路。 检查半导体衬底背面上的多个导电通孔以确定半导体衬底背面上的多个导电通孔中的至少两个的部分的位置。 从确定的位置确定半导体衬底的x-y空间取向。 考虑了其他方面和实现。

公开(公告)号：US20120229908A1

公开(公告)日：2012-09-13

申请号：US13481329

申请日：2012-05-25

Applicant: Gregory J. Kintz ,  Michael R. Feldman ,  James E. Morris ,  Paul Elliott ,  David Keller ,  W. Hudson Welch ,  David Ovrutsky ,  Jeremy Huddleston ,  Mark Hiatt

Inventor： Gregory J. Kintz ,  Michael R. Feldman ,  James E. Morris ,  Paul Elliott ,  David Keller ,  W. Hudson Welch ,  David Ovrutsky ,  Jeremy Huddleston ,  Mark Hiatt

IPC: G02B27/12

CPC classification number: B29D11/00365 ,  B29D11/00413 ,  G02B3/0031 ,  G02B3/0062

Abstract: An optics block includes a substrate having first and second opposing surfaces, the substrate being a first material, a plurality of through holes extending in the substrate between the first and second opposing surface, a second material, different than the first material, filling a portion of the through holes and extending on a portion of the first surface of the substrate outside the through holes, and a first lens structure in the second material and corresponding to each of the through holes.

Abstract translation: 光学块包括具有第一和第二相对表面的基板，所述基板是第一材料，在所述基板中在所述第一和第二相对表面之间延伸的多个通孔，与所述第一材料不同的第二材料， 的通孔，并且在通孔的外部的基板的第一表面的一部分上延伸，以及在第二材料中的第一透镜结构，并且对应于每个通孔。

公开(公告)号：US08189277B2

公开(公告)日：2012-05-29

申请号：US13050354

申请日：2011-03-17

Applicant: Gregory J. Kintz ,  Michael R. Feldman ,  James E. Morris ,  Paul Elliott ,  David Keller ,  W. Hudson Welch ,  David Ovrutsky ,  Jeremy Huddleston ,  Mark Hiatt

Inventor： Gregory J. Kintz ,  Michael R. Feldman ,  James E. Morris ,  Paul Elliott ,  David Keller ,  W. Hudson Welch ,  David Ovrutsky ,  Jeremy Huddleston ,  Mark Hiatt

IPC: G02B27/00

CPC classification number: B29D11/00365 ,  B29D11/00413 ,  G02B3/0031 ,  G02B3/0062

Abstract: An optics block includes a substrate having first and second opposing surfaces, the substrate being a first material, a plurality of through holes extending in the substrate between the first and second opposing surface, a second material, different than the first material, filling a portion of the through holes and extending on a portion of the first surface of the substrate outside the through holes, and a first lens structure in the second material and corresponding to each of the through holes.

Abstract translation: 光学块包括具有第一和第二相对表面的基板，所述基板是第一材料，在所述基板中在所述第一和第二相对表面之间延伸的多个通孔，与所述第一材料不同的第二材料， 的通孔，并且在通孔的外部的基板的第一表面的一部分上延伸，以及在第二材料中的第一透镜结构，并且对应于每个通孔。

公开(公告)号：US07956443B2

公开(公告)日：2011-06-07

申请号：US12725724

申请日：2010-03-17

Applicant: Salman Akram ,  Charles M. Watkins ,  Mark Hiatt ,  David R. Hembree ,  James M. Wark ,  Warren M. Farnworth ,  Mark E. Tuttle ,  Sidney B. Rigg ,  Steven D. Oliver ,  Kyle K. Kirby ,  Alan G. Wood ,  Lu Velicky

Inventor： Salman Akram ,  Charles M. Watkins ,  Mark Hiatt ,  David R. Hembree ,  James M. Wark ,  Warren M. Farnworth ,  Mark E. Tuttle ,  Sidney B. Rigg ,  Steven D. Oliver ,  Kyle K. Kirby ,  Alan G. Wood ,  Lu Velicky

IPC: H01L23/485

CPC classification number: H01L21/76877 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/45 ,  H01L27/14634 ,  H01L27/14636 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Abstract translation: 公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。 此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

公开(公告)号：US07189954B2

公开(公告)日：2007-03-13

申请号：US10894262

申请日：2004-07-19

Applicant: Warren M. Farnworth ,  Sidney B. Rigg ,  William Mark Hiatt ,  Alan G. Wood ,  Peter A. Benson ,  James M. Wark ,  David R. Hembree ,  Kyle K. Kirby ,  Charles M. Watkins ,  Salman Akram

Inventor： Warren M. Farnworth ,  Sidney B. Rigg ,  William Mark Hiatt ,  Alan G. Wood ,  Peter A. Benson ,  James M. Wark ,  David R. Hembree ,  Kyle K. Kirby ,  Charles M. Watkins ,  Salman Akram

IPC: H01L31/0232 ,  H01L27/00

CPC classification number: H01L27/00 ,  B33Y80/00 ,  H01L27/14618 ,  H01L27/14625 ,  H01L27/14683 ,  H01L27/14687 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/00014

Abstract: Microelectronic imager assemblies comprising a workpiece including a substrate and a plurality of imaging dies on and/or in the substrate. The substrate includes a front side and a back side, and the imaging dies comprise imaging sensors at the front side of the substrate and external contacts operatively coupled to the image sensors. The microelectronic imager assembly further comprises optics supports superimposed relative to the imaging dies. The optics supports can be directly on the substrate or on a cover over the substrate. Individual optics supports can have (a) an opening aligned with one of the image sensors, and (b) a bearing element at a reference distance from the image sensor. The microelectronic imager assembly can further include optical devices mounted or otherwise carried by the optics supports.