公开(公告)号：US20190214480A1

公开(公告)日：2019-07-11

申请号：US16357333

申请日：2019-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chien Hsieh ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Po-Wen Su

IPC: H01L29/66 ,  H01L21/266 ,  H01L21/265 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7851

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.

公开(公告)号：US20180261589A1

公开(公告)日：2018-09-13

申请号：US15980759

申请日：2018-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Kuei-Chun Hung

IPC: H01L27/02 ,  H01L27/11582 ,  H01L21/3213

CPC classification number: H01L27/0207 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.

公开(公告)号：US20180047635A1

公开(公告)日：2018-02-15

申请号：US15264590

申请日：2016-09-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung ,  Chih-Wei Yang

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, and a spacer. The semiconductor substrate includes at least one fin structure. The isolation structure is partly disposed in the fin structure and partly disposed above the fin structure. The fin structure includes a first fin and a second fin elongated in the same direction. A part of the isolation structure is disposed between the first fin and the second fin in the direction where the first fin and the second fin are elongated. The spacer is disposed on sidewalls of the isolation structure on the fin structure. The isolation structure in the present invention is partly disposed in the fin structure and partly disposed above the fin structure. The negative influence of a gate structure formed on the isolation structure and sinking into the isolation structure on the isolation performance of the isolation structure may be avoided accordingly.

公开(公告)号：US09660022B2

公开(公告)日：2017-05-23

申请号：US14830756

申请日：2015-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chia-Hsun Tseng

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/764 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A method of fabricating a single diffusion break includes providing a fin with two gate structures crossing the fin and a middle dummy gate structure crossing the fin, wherein the middle dummy gate structure is sandwiched by the gate structures. Later, numerous spacers are formed and each spacer respectively surrounds the gate structures and the middle dummy gate structure. Then, the middle dummy gate structure, and part of the fin directly under the middle dummy gate structure are removed to form a recess. Finally, an isolating layer in the recess is formed to close an entrance of the recess so as to form a void embedded within the recess.

公开(公告)号：US20170117151A1

公开(公告)日：2017-04-27

申请号：US14945443

申请日：2015-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Kuei-Chun Hung

IPC: H01L21/033 ,  H01L27/02

CPC classification number: H01L27/0207 ,  H01L21/32139 ,  H01L27/11582 ,  H01L28/00

Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.

公开(公告)号：US09607892B2

公开(公告)日：2017-03-28

申请号：US15201511

申请日：2016-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Chih-Sen Huang ,  Yu-Cheng Tung

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/66 ,  H01L21/308 ,  H01L23/522 ,  H01L23/485 ,  H01L29/66 ,  H01L29/00

CPC classification number: H01L21/76895 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/3085 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/00 ,  H01L29/66545 ,  H01L29/66553

Abstract: A method for fabricating semiconductor device comprising: providing a substrate having a gate structure thereon and a first interlayer dielectric (ILD) layer surrounding the gate structure; removing part of the gate structure; forming a first mask layer on the first ILD layer and the gate structure; removing the first mask layer on the first ILD layer and part of the first mask layer on the gate structure for forming a first hard mask on the gate structure; forming a second mask layer on the first ILD layer, the first hard mask, and the gate structure; and planarizing the second mask layer to form a second hard mask on the gate structure, in which the top surfaces of the first hard mask, the second hard mask, and the first ILD layer are coplanar.

公开(公告)号：US20170040415A1

公开(公告)日：2017-02-09

申请号：US14840038

申请日：2015-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Chun-Yuan Wu

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/283 ,  H01L21/308 ,  H01L21/311 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/76232 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a plurality of fin-shaped structures and a first shallow trench isolation (STI) around the fin-shaped structures on the first region and the second region; forming a patterned hard mask on the second region; removing the fin-shaped structures and the first STI from the first region; forming a second STI on the first region; removing the patterned hard mask; and forming a gate structure on the second STI.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有第一区域和第二区域的衬底; 在所述第一区域和所述第二区域上的所述鳍状结构周围形成多个鳍状结构和第一浅沟槽隔离（STI）; 在所述第二区域上形成图案化的硬掩模; 从所述第一区域去除所述鳍状结构和所述第一STI; 在所述第一区域上形成第二STI; 去除图案化的硬掩模; 以及在第二STI上形成栅极结构。

公开(公告)号：US20160204197A1

公开(公告)日：2016-07-14

申请号：US14612300

申请日：2015-02-03

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Ssu-I Fu ,  Chia-Lin Lu ,  Shih-Hung Tsai ,  Chih-Wei Yang ,  Chia-Ching Lin ,  Chia-Hsun Tseng ,  Rai-Min Huang

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0684 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76232 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7846 ,  H01L29/7851

Abstract: The present invention provides a semiconductor structure, including a substrate, a shallow trench isolation (STI) disposed in the substrate, a plurality of first fin structures disposed in the substrate, where each first fin structure and the substrate have same material, and a plurality of second fin structures disposed in the STI, where each second fin structure and the STI have same material.

Abstract translation: 本发明提供一种半导体结构，包括基板，设置在基板中的浅沟槽隔离（STI），设置在基板中的多个第一翅片结构，其中每个第一翅片结构和基板具有相同的材料，以及多个 设置在STI中的第二鳍结构，其中每个第二鳍结构和STI具有相同的材料。

公开(公告)号：US09349822B2

公开(公告)日：2016-05-24

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/321 ,  H01L27/092

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US20160093536A1

公开(公告)日：2016-03-31

申请号：US14520342

申请日：2014-10-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  Yu-Ru Yang ,  En-Chiuan Liou

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/423 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

Abstract: The present invention provides an integrated circuit including a substrate, a first transistor, a second transistor and a third transistor. The first transistor has a first metal gate including a first bottom barrier layer, a first work function metal layer and a first metal layer. The second transistor has a second metal gate including a second bottom barrier layer, a second work function metal layer and a second metal layer. The third transistor has a third metal gate including a third bottom barrier layer, a third work function metal layer and a third metal layer. The first transistor, the second transistor and the third transistor has the same conductive type. A nitrogen concentration of the first bottom barrier layer>a nitrogen concentration of the second bottom barrier layer>a nitrogen concentration of the third bottom barrier layer.

Abstract translation: 本发明提供一种集成电路，其包括衬底，第一晶体管，第二晶体管和第三晶体管。 第一晶体管具有包括第一底部阻挡层，第一功函数金属层和第一金属层的第一金属栅极。 第二晶体管具有包括第二底部阻挡层，第二功函数金属层和第二金属层的第二金属栅极。 第三晶体管具有包括第三底部阻挡层，第三功函数金属层和第三金属层的第三金属栅极。 第一晶体管，第二晶体管和第三晶体管具有相同的导电类型。 第一底部阻挡层的氮浓度>第二底部阻挡层的氮浓度>第三底部阻挡层的氮浓度。