公开(公告)号：US20210050456A1

公开(公告)日：2021-02-18

申请号：US16572556

申请日：2019-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.

公开(公告)号：US10529825B2

公开(公告)日：2020-01-07

申请号：US15951147

申请日：2018-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chi-Ting Wu ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source/drain region, a source/drain contact structure, a first dielectric layer, a first spacer, and a first connection structure. The gate structure is disposed on the semiconductor substrate. The source/drain region is disposed in the semiconductor substrate and disposed at a side of the gate structure. The source/drain contact structure is disposed on the source/drain region. The first dielectric layer is disposed on the source/drain contact structure and the gate structure. The first spacer is disposed in a first contact hole penetrating the first dielectric layer on the source/drain contact structure. The first connection structure is disposed in the first contact hole. The first connection structure is surrounded by the first spacer in the first contact hole, and the first connection structure is connected with the source/drain contact structure.

公开(公告)号：US20190221469A1

公开(公告)日：2019-07-18

申请号：US15873838

申请日：2018-01-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.

公开(公告)号：US10249488B1

公开(公告)日：2019-04-02

申请号：US15866489

申请日：2018-01-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chi-Ting Wu ,  Yu-Hsiang Lin

IPC: H01L21/02 ,  H01L21/67 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L27/088 ,  H01L29/165

Abstract: A semiconductor device with three transistors of same conductive type but different threshold voltage is provided in the present invention, wherein the first transistor includes a high-k dielectric layer, a first bottom barrier metal layer, a second bottom barrier metal layer, a work function metal layer and a low resistance metal. The second transistor includes the high-k dielectric layer, the first bottom barrier metal layer, the second bottom barrier metal layer and the low resistance metal, and a third transistor on the substrate. The third transistor includes the high-k dielectric layer, the first bottom barrier metal layer and the low resistance metal.