公开(公告)号：US20140295660A1

公开(公告)日：2014-10-02

申请号：US14302047

申请日：2014-06-11

Applicant: United Microelectronics Corp.

Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Chien-Ting Lin ,  Wen-Tai Chiang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/28

CPC classification number: H01L29/6681 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/283 ,  H01L21/76224 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device is provided. A first interfacial material layer is formed by a deposition process on a substrate. A dummy gate material layer is formed on the first interfacial material layer. The dummy gate material layer and the first interfacial material layer are patterned to form a stacked structure. An interlayer dielectric (ILD) layer is formed to cover the stacked structure. A portion of the ILD layer is removed to expose a top of the stacked structure. The stacked structure is removed to form a trench in the ILD layer. A second interfacial layer and a first high-k layer are conformally foamed at least on a surface of the trench. A composite metal layer is formed to at least fill up the trench.

Abstract translation: 提供一种形成半导体器件的方法。 通过在衬底上的沉积工艺形成第一界面材料层。 在第一界面材料层上形成虚拟栅极材料层。 将虚拟栅材料层和第一界面材料层图案化以形成堆叠结构。 形成层间电介质（ILD）层以覆盖层叠结构。 去除ILD层的一部分以露出堆叠结构的顶部。 去除层叠结构以在ILD层中形成沟槽。 第二界面层和第一高k层至少在沟槽的表面上保形发泡。 复合金属层形成为至少填充沟槽。

公开(公告)号：US20140235043A1

公开(公告)日：2014-08-21

申请号：US13772343

申请日：2013-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin ,  Shih-Hung Tsai

IPC: H01L21/28

CPC classification number: H01L29/7853 ,  H01L29/66795

Abstract: A method for forming a fin-shaped structure includes the following steps. A pad layer is formed on a substrate. A sacrificial pattern is formed on the pad layer. A spacer is formed on the pad layer beside the sacrificial pattern, wherein the ratio of the height of the spacer to the pad layer is larger than 5. The sacrificial pattern is removed. The layout of the spacer is transferred to the substrate to form at least a fin-shaped structure having a taper profile in the substrate.

Abstract translation: 形成翅片状结构的方法包括以下步骤。 衬底层形成在衬底上。 牺牲图案形成在衬垫层上。 在牺牲图案旁边的垫层上形成间隔物，其中间隔物与垫层的高度比大于5.牺牲图案被去除。 间隔物的布局被转移到基底以至少形成在基底中具有锥形轮廓的鳍状结构。

公开(公告)号：US08779513B2

公开(公告)日：2014-07-15

申请号：US13869037

申请日：2013-04-24

Applicant: United Microelectronics Corp.

Inventor： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.

Abstract translation: 非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。 鳍状结构位于基底上。 隔离结构位于鳍状结构之间，隔离结构具有含氮层。 外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。 还提供了用于形成半导体结构的非平面半导体工艺。

公开(公告)号：US20130252387A1

公开(公告)日：2013-09-26

申请号：US13895376

申请日：2013-05-16

Applicant: United Microelectronics Corp.

Inventor： Shih-Hung Tsai ,  Wen-Tai Chiang ,  Chen-Hua Tsai ,  Cheng-Tzung Tsai

IPC: H01L21/8234

CPC classification number: H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843

Abstract: A method for fabricating a metal-gate CMOS device. A substrate having thereon a first region and a second region is provided. A first dummy gate structure and a second dummy gate structure are formed within the first region and the second region respectively. A first LDD is formed on either side of the first dummy gate structure and a second LDD is formed on either side of the second dummy gate structure. A first spacer is formed on a sidewall of the first dummy gate structure and a second spacer is formed on a sidewall of the second dummy gate structure. A first embedded epitaxial layer is then formed in the substrate adjacent to the first dummy gate structure. The first region is masked with a seal layer. Thereafter, a second embedded epitaxial layer is formed in the substrate adjacent to the second dummy gate structure.

Abstract translation: 一种制造金属栅CMOS器件的方法。 提供其上具有第一区域和第二区域的基板。 第一虚拟栅极结构和第二虚拟栅极结构分别形成在第一区域和第二区域内。 第一LDD形成在第一虚拟栅极结构的两侧，第二LDD形成在第二虚拟栅极结构的任一侧上。 第一间隔物形成在第一伪栅极结构的侧壁上，第二间隔物形成在第二虚拟栅极结构的侧壁上。 然后在与第一伪栅极结构相邻的衬底中形成第一嵌入式外延层。 第一区域用密封层掩蔽。 此后，在与第二虚拟栅极结构相邻的衬底中形成第二嵌入式外延层。

公开(公告)号：US12114508B2

公开(公告)日：2024-10-08

申请号：US17548607

申请日：2021-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Chun-Hsien Lin

IPC: H10B53/30

CPC classification number: H10B53/30

Abstract: A method for fabricating a semiconductor device includes the steps of forming a first inter-metal dielectric (IMD) layer on a substrate, forming a first trench and a second trench in the first IMD layer, forming a bottom electrode in the first trench and the second trench, forming a ferroelectric (FE) layer on the bottom electrode, and then forming a top electrode on the FE layer to form a ferroelectric random access memory (FeRAM).

公开(公告)号：US12041784B2

公开(公告)日：2024-07-16

申请号：US17491509

申请日：2021-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Hon-Huei Liu ,  Chun-Hsien Lin

IPC: H10B53/30 ,  H01L27/12 ,  H01L27/13 ,  H10B51/00

CPC classification number: H10B53/30 ,  H01L27/1207 ,  H01L27/13

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal-oxide semiconductor (MOS) transistor on a substrate, forming an interlayer dielectric (ILD) layer on the MOS transistor, forming a ferroelectric field effect transistor (FeFET) on the ILD layer, and forming a ferroelectric random access memory (FeRAM) on the ILD layer. The formation of the FeFET further includes first forming a semiconductor layer on the ILD layer, forming a gate structure on the semiconductor layer, and then forming a source/drain region adjacent to the gate structure.

公开(公告)号：US11705498B2

公开(公告)日：2023-07-18

申请号：US17185985

申请日：2021-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/66045 ,  H01L29/78696

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

公开(公告)号：US20230215855A1

公开(公告)日：2023-07-06

申请号：US17673749

申请日：2022-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Chien-Ting Lin ,  Yu-Hsiang Lin ,  Ssu-I Fu ,  Chih-Kai Hsu

IPC: H01L25/18 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L25/50 ,  H01L25/0657 ,  H01L24/08

Abstract: A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

公开(公告)号：US20220238677A1

公开(公告)日：2022-07-28

申请号：US17185985

申请日：2021-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66

Abstract: A method for fabricating a nanowire transistor includes the steps of first forming a nanowire channel structure on a substrate, in which the nanowire channel structure includes first semiconductor layers and second semiconductor layers alternately disposed over one another. Next, a gate structure is formed on the nanowire channel structure and then a source/drain structure is formed adjacent to the gate structure, in which the source/drain structure is made of graphene.

公开(公告)号：US20210351211A1

公开(公告)日：2021-11-11

申请号：US16871017

申请日：2020-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai

IPC: H01L27/146

Abstract: A single photon avalanche diode includes a silicon-on-insulator (SOI) substrate having a base substrate, a buried oxide layer over the base substrate, and a silicon layer over the buried oxide layer. At least one photodiode region is disposed in the base substrate. The photodiode region comprises an epitaxial layer embedded in the base substrate.