公开(公告)号：US20190378971A1

公开(公告)日：2019-12-12

申请号：US16029641

申请日：2018-07-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H01L43/02 ,  H01L27/22 ,  H01L27/02 ,  G11C11/16

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

公开(公告)号：US10355048B1

公开(公告)日：2019-07-16

申请号：US15920008

申请日：2018-03-13

Applicant: United Microelectronics Corp.

Inventor： Chung-Liang Chu ,  Yu-Ruei Chen ,  Hung-Yueh Chen ,  Yu-Ping Wang

IPC: H01L27/22 ,  H01L21/76 ,  H01L29/78 ,  G11C11/16 ,  H01L29/06 ,  H01L21/762 ,  H01L43/12 ,  H01L43/02 ,  H01L21/3205 ,  H01F10/32 ,  H01L43/08

Abstract: An isolation structure is disposed between fin field effect transistors of a magnetic random access memory (MRAM) device. The isolation structure includes a fin line substrate, having a trench crossing the fin line substrate. An oxide layer is disposed on the fin line substrate other than the trench. A liner layer is disposed on an indent surface of the trench. A nitride layer is disposed on the liner layer, partially filling the trench. An oxide residue is disposed on the nitride layer within the trench at a bottom portion of the trench. A gate-like structure is disposed on the oxide layer and also fully filling the trench.

公开(公告)号：US10008581B2

公开(公告)日：2018-06-26

申请号：US14840041

申请日：2015-08-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Tsen Lu ,  Chien-Ming Lai ,  Lu-Sheng Chou ,  Ya-Huei Tsai ,  Ching-Hsiang Chiu ,  Yu-Tung Hsiao ,  Chen-Ming Huang ,  Kun-Ju Li ,  Yu-Ping Wang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  C22C32/00 ,  H01L29/51 ,  H01L21/28 ,  B32B1/00

CPC classification number: H01L29/66545 ,  B32B1/00 ,  B32B18/00 ,  C22C32/0068 ,  H01L21/28088 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/511

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and a gate structure on the substrate. The gate structure includes a high-k dielectric layer on the substrate and a bottom barrier metal (BBM) layer on the high-k dielectric layer. Preferably, the BBM layer includes a top portion, a middle portion, and a bottom portion, in which the top portion being a nitrogen rich portion, and the middle portion and the bottom portion being titanium rich portions.

公开(公告)号：US09721840B2

公开(公告)日：2017-08-01

申请号：US15194577

申请日：2016-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Chien-Chung Huang ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L21/283 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/823437 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/3211 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

公开(公告)号：US20160307805A1

公开(公告)日：2016-10-20

申请号：US15194577

申请日：2016-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Chien-Chung Huang ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/283 ,  H01L21/321

CPC classification number: H01L21/823437 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/3211 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供一种互补金属氧化物半导体器件，其包括PMOS和NMOS。 PMOS具有P型金属栅极，其包括底部阻挡层，P功函数金属（PWFM）层，N功函数调整（NWFT）层，N功函数金属（NWFM）层和金属层。 NMOS具有N型金属栅极，其包括NWFT层，NWFM层和低电阻层。 本发明还提供一种形成该方法的方法。

公开(公告)号：US09379242B1

公开(公告)日：2016-06-28

申请号：US14723476

申请日：2015-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Mon-Sen Lin ,  Yu-Ping Wang ,  Yu-Ting Tseng ,  Hao-Yeh Liu ,  Chun-tsen Lu

IPC: H01L21/4763 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L29/7847 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of fabricating a fin field effect transistor including providing a substrate having at least one fin structure, a dummy gate, and an internal dielectric layer thereon, removing the dummy gate to form a gate trench on the fin structure, blanketly forming a stress film on the substrate to cover a surface of the gate trench, performing a thermal annealing process, removing the stress film, and forming a metal gate is in the gate trench.

Abstract translation: 一种制造鳍状场效应晶体管的方法，包括：在其上提供具有至少一个鳍结构的衬底，伪栅极和内部电介质层，去除所述虚设栅极以在所述鳍结构上形成栅极沟槽，以覆盖形式施加应力膜 在基板上覆盖栅极沟槽的表面，执行热退火处理，去除应力膜和形成金属栅极在栅极沟槽中。

公开(公告)号：US20250113742A1

公开(公告)日：2025-04-03

申请号：US18979539

申请日：2024-12-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yu-Ping Wang

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

公开(公告)号：US12268098B2

公开(公告)日：2025-04-01

申请号：US18528707

申请日：2023-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H10N50/80 ,  G11C11/16 ,  H01L27/02 ,  H10B61/00

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

公开(公告)号：US12201032B2

公开(公告)日：2025-01-14

申请号：US17223025

申请日：2021-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H10N50/85 ,  H10B61/00 ,  H10N50/80 ,  H10N50/01

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.

公开(公告)号：US12150313B2

公开(公告)日：2024-11-19

申请号：US18500994

申请日：2023-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  I-Fan Chang ,  Rai-Min Huang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.