公开(公告)号：US20230067112A1

公开(公告)日：2023-03-02

申请号：US17983396

申请日：2022-11-09

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min Tain ,  John Hon-Shing Lau ,  Pu-Ju Lin ,  Wei-Ci Ye ,  Chi-Hai Kuo ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng

IPC: F28D15/04 ,  F28D15/02 ,  F28F3/10 ,  B23P15/26 ,  F28F21/08

Abstract: A vapor chamber structure includes a thermally conductive shell, a capillary structure layer, and a working fluid. The thermally conductive shell includes a first thermally conductive portion and a second thermally conductive portion. The first thermally conductive portion and the second thermally conductive portion are a thermally conductive plate that is integrally formed, and the thermally conductive shell is formed by folding the thermally conductive plate in half and then sealing the thermally conductive plate. The first thermally conductive portion has at least one first cavity, the second thermally conductive portion has at least one second cavity. At least one sealed chamber is defined between the thermally conductive plate, the first cavity and the second cavity. A pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer covers an inner wall of the sealed chamber. The working fluid is filled in the sealed chamber.

公开(公告)号：US11476234B2

公开(公告)日：2022-10-18

申请号：US16846429

申请日：2020-04-13

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L25/075 ,  H01L33/62 ,  H01L33/00 ,  H01L33/52

Abstract: A manufacturing method of chip package structure includes following steps. A carrier is provided. A first patterned circuit layer and a first dielectric layer covering the first patterned circuit layer have been formed on the carrier. A flat structure layer is formed on the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and covers the flat structure layer and a portion of the first dielectric layer. A second patterned circuit layer is formed on the second dielectric layer. The second patterned circuit layer includes a plurality of pads. An orthographic projection of the flat structure layer on the carrier overlaps orthographic projections of the pads on the carrier. A plurality of chips are disposed on the pads. A molding compound is formed to cover the second dielectric layer and encapsulate the chips and the pads.

公开(公告)号：US11460255B2

公开(公告)日：2022-10-04

申请号：US17113332

申请日：2020-12-07

Applicant: UNIMICRON TECHNOLOGY CORP.

Inventor： Pu-Ju Lin ,  Ying-Chu Chen ,  Wei-Ci Ye ,  Chi-Hai Kuo ,  Cheng-Ta Ko

IPC: B23P15/26 ,  F28D15/04 ,  C23F17/00 ,  H05K7/20 ,  H01L23/427

Abstract: A vapor chamber device and a manufacturing method are disclosed. The vapor chamber has a housing and multiple independent chambers. The housing includes two shells opposite to each other. The independent chambers are formed between the two shells. Each independent chamber contains a working fluid and has at least one diversion bump and a capillary structure. The diversion bump is formed on an inner surface of the second shell, and the capillary structure is mounted on the diversion bump. When the vapor chamber device is vertically mounted to a heat source, the independent chambers at an upper portion of the vapor chamber device still contain the working fluid. The working fluid in the independent chambers may not all flow to a bottom of the vapor chamber device. Therefore, a contact area between the working fluid and the heat source is increased and heat dissipation efficiency is improved.

公开(公告)号：US20220256717A1

公开(公告)日：2022-08-11

申请号：US17234805

申请日：2021-04-20

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Cheng-Ta Ko ,  Pu-Ju Lin ,  Chi-Hai Kuo ,  Kai-Ming Yang ,  Chia-Yu Peng ,  Shao-Chien Lee ,  Tzyy-Jang Tseng

IPC: H05K3/46 ,  H05K3/02 ,  H05K3/40 ,  H05K3/38

Abstract: A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.

公开(公告)号：US20220208631A1

公开(公告)日：2022-06-30

申请号：US17156626

申请日：2021-01-24

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Kai-Ming Yang ,  Cheng-Ta Ko

IPC: H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

Abstract: A chip package structure including a chip, a stress buffer layer, a first insulating layer, a redistribution layer, a second insulating layer, and a solder ball is provided. The chip has an active surface, a back surface and a peripheral surface. The stress buffer layer covers the active surface and the peripheral surface, and the first insulating layer is disposed on the back surface. A bottom surface of the stress buffer layer is aligned with the back surface of the chip. The redistribution layer is electrically connected to the chip through an opening of the stress buffer layer. The second insulating layer covers the stress buffer layer and the redistribution layer. The solder ball is disposed in a blind hole of the second insulating layer and electrically connected to the redistribution layer. A top surface of the solder ball protrudes from an upper surface of the second insulating layer.

公开(公告)号：US20220059498A1

公开(公告)日：2022-02-24

申请号：US17098436

申请日：2020-11-15

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Pu-Ju Lin ,  Cheng-Ta Ko ,  Ra-Min Tain

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L23/48

Abstract: A chip package structure includes a substrate, a first chip, a second chip, a bridge, a plurality of first bumps, a plurality of second bumps, a plurality of third bumps and a plurality of solder balls. A first active surface of the first chip and a second active surface of the second chip face a first surface of the substrate. The bridge includes a high-molecular polymer layer and a pad layer located on the high-molecular polymer layer. The first chip is electrically connected to the substrate through the first bumps. The second chip is electrically connected to the substrate through the second bumps. The first chip and the second chip are electrically connected to the pad layer through the third bumps. The first bumps and the second bumps have the same size. The solder balls are disposed on a second surface of the substrate and electrically connected to the substrate.

公开(公告)号：US20210282275A1

公开(公告)日：2021-09-09

申请号：US16847688

申请日：2020-04-14

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming Yang ,  Chen-Hao Lin ,  Pu-Ju Lin

IPC: H05K3/46 ,  H05K3/22 ,  H05K1/02

Abstract: A wiring board including a build-up circuit layer, a patterned conductive layer, first and second adhesion promoting material layers and first and second solder mask layers is provided. The build-up circuit layer has a first surface and a second surface opposite thereto. The patterned conductive layer is disposed on the second surface. The first adhesion promoting material layer is disposed on the first surface and includes at least one first opening. The second adhesion promoting material layer is disposed on the second surface and the patterned conductive layer, and includes at least one second opening. The first solder mask layer is disposed on the first adhesion promoting material layer and includes at least one third opening provided corresponding to the first opening. The second solder mask layer is disposed on the second adhesion promoting material layer and includes at least one fourth opening provided corresponding to the second opening.

公开(公告)号：US20210247147A1

公开(公告)日：2021-08-12

申请号：US17168200

申请日：2021-02-05

Applicant: Unimicron Technology Corp.

Inventor： Ra-Min Tain ,  John Hon-Shing Lau ,  Pu-Ju Lin ,  Wei-Ci Ye ,  Chi-Hai Kuo ,  Cheng-Ta Ko ,  Tzyy-Jang Tseng

IPC: F28D15/04 ,  F28D15/02 ,  F28F21/08 ,  F28F3/10 ,  B23P15/26

Abstract: A vapor chamber structure including a thermally conductive shell, a capillary structure layer, and a working fluid is provided. The thermally conductive shell includes a first thermally conductive portion and a second thermally conductive portion. The first thermally conductive portion has at least one first cavity. The second thermally conductive portion and the first cavity define at least one sealed chamber, and a pressure in the sealed chamber is lower than a standard atmospheric pressure. The capillary structure layer covers an inner wall of the sealed chamber. The working fluid is filled in the sealed chamber.