公开(公告)号：US20170194193A1

公开(公告)日：2017-07-06

申请号：US15465606

申请日：2017-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Yi Chiu ,  Shih-Fang Hong ,  Chao-Hung Lin

IPC: H01L21/762 ,  H01L29/161 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure is disposed on the silicon substrate and includes a silicon germanium (SiGe) layer extending from bottom to top in the fin shaped structure. The shallow trench isolation covers a bottom portion of the fin shaped structure.

公开(公告)号：US09659873B2

公开(公告)日：2017-05-23

申请号：US14836947

申请日：2015-08-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Chiao Wang ,  Yu-Hsiang Hung ,  Chao-Hung Lin ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L29/06 ,  H01L21/765 ,  H01L21/762 ,  G03F9/00 ,  H01L23/544 ,  H01L21/28 ,  H01L21/311 ,  H01L21/033

CPC classification number: H01L23/544 ,  H01L21/0337 ,  H01L21/28008 ,  H01L21/28132 ,  H01L21/32139 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5446

Abstract: The present invention provides a semiconductor structure comprising a wafer and an aligning mark. The wafer has a dicing region which comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. The aligning mark is disposed in the dicing region, wherein the alignment mark is a mirror symmetrical pattern. The aligning mark comprises a plurality of second patterns in the middle region and a plurality of third patterns disposed in peripheral region, wherein each third pattern comprises a plurality of lines, and a width of the line is 10 times less than a width of the L-shapes. The present invention further provides a method of forming the same.

公开(公告)号：US09653290B2

公开(公告)日：2017-05-16

申请号：US15378015

申请日：2016-12-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Shih-Fang Hong ,  Chao-Hung Lin ,  Jyh-Shyang Jenq

IPC: H01L21/20 ,  H01L27/12 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L21/02603 ,  H01L21/823807 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

Abstract: A method for manufacturing a nanowire transistor device includes the following steps: A substrate is provided, and the substrate includes a plurality of nanowires suspended thereon. Each of the nanowires includes a first semiconductor core. Next, a first selective epitaxial growth process is performed to form second semiconductor cores respectively surrounding the first semiconductor cores. The second semiconductor cores are spaced apart from the substrate. After forming the second semiconductor core, a gate is formed on the substrate.

公开(公告)号：US20170040318A1

公开(公告)日：2017-02-09

申请号：US14842855

申请日：2015-09-02

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Chao-Hung Lin ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/45 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/0649 ,  H01L29/45

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure on a first region and a second fin-shaped structure on a second region; forming a plurality of first gate structures on the first fin-shaped structure, a plurality of second gate structures on the second fin-shaped structure, and an interlayer dielectric (ILD) layer around the first gate structures and the second gate structures; forming a first patterned mask on the ILD layer; forming a second patterned mask on the second region; using the first patterned mask and the second patterned mask to remove all of the ILD layer from the first region and part of the ILD layer from the second region for forming a plurality of first contact holes in the first region and a plurality of second contact holes in the second region.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：在第一区域上提供具有第一鳍状结构的基底和在第二区域上提供第二鳍状结构; 在所述第一鳍状结构上形成多个第一栅极结构，在所述第二鳍状结构上形成多个第二栅极结构，以及围绕所述第一栅极结构和所述第二栅极结构的层间电介质（ILD）层; 在ILD层上形成第一图案化掩模; 在所述第二区域上形成第二图案化掩模; 使用第一图案化掩模和第二图案化掩模从第二区域从第一区域和ILD层的一部分去除所有ILD层，用于在第一区域中形成多个第一接触孔，以及多个第二接触孔 在第二个地区。

公开(公告)号：US20170033019A1

公开(公告)日：2017-02-02

申请号：US15294797

申请日：2016-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Hon-Huei Liu ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/225

CPC classification number: H01L21/823821 ,  H01L21/2255 ,  H01L21/2256 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/66803 ,  H01L29/7851

Abstract: A semiconductor device includes: a fin-shaped structure on a substrate, in which the fin-shaped structure includes a top portion and a bottom portion; a doped layer around the bottom portion of the fin-shaped structure; a first liner on the doped layer, and a second liner on the top portion and the bottom portion of the fin-shaped structure. Preferably, the first liner and the second liner are made of different material.

Abstract translation: 半导体器件包括：在基板上的鳍状结构，其中鳍状结构包括顶部和底部; 围绕所述鳍状结构的底部的掺杂层; 在掺杂层上的第一衬垫，以及鳍状结构的顶部和底部上的第二衬垫。 优选地，第一衬垫和第二衬套由不同的材料制成。

公开(公告)号：US20170005008A1

公开(公告)日：2017-01-05

申请号：US14814516

申请日：2015-07-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chao-Hung Lin ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L29/06 ,  H01L21/308 ,  H01L21/28 ,  H01L21/762 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/28123 ,  H01L21/3086 ,  H01L21/762 ,  H01L21/76232 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: A method for fabricating a semiconductor device having a gate structure includes forming a substrate including at least two fin structures protruding from a top surface of the substrate, the substrate including a first recess and a second recess disposed under the first recess, and the first recess and the second recess being disposed between the fin structures, wherein a width of the first recess is larger than a width of the second recess, and the first recess and the second recess form a step structure; forming an insulating structure in the second recess; and forming the gate structure on the insulating structure, wherein the first recess and the second recess are filled up with the gate structure and the insulating structure.

Abstract translation: 一种用于制造具有栅极结构的半导体器件的方法，包括形成包括至少两个鳍状结构的衬底，所述鳍结构从衬底的顶表面突出，所述衬底包括第一凹部和设置在第一凹部下方的第二凹部， 并且所述第二凹部设置在所述翅片结构之间，其中所述第一凹部的宽度大于所述第二凹部的宽度，并且所述第一凹部和所述第二凹部形成台阶结构; 在所述第二凹部中形成绝缘结构; 以及在所述绝缘结构上形成所述栅极结构，其中所述第一凹槽和所述第二凹槽被所述栅极结构和所述绝缘结构填充。

公开(公告)号：US09530778B1

公开(公告)日：2016-12-27

申请号：US14834439

申请日：2015-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chao-Hung Lin ,  Chih-Kai Hsu ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Chien-Ting Lin ,  Jyh-Shyang Jenq ,  Ching-Wen Hung ,  Jia-Rong Wu ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-Kuan Wu ,  Chih-Sen Huang ,  Yi-Wei Chen

IPC: H01L21/00 ,  H01L27/092 ,  H01L29/51 ,  H01L21/8238

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/511 ,  H01L29/517

Abstract: Semiconductor devices having metal gate include a substrate, a first nFET device formed thereon, and a second nFET device formed thereon. The first nFET device includes a first n-metal gate, and the first n-metal gate includes a third bottom barrier metal layer and an n type work function metal layer. The n type work function metal layer directly contacts the third bottom barrier layer. The second nFET device includes a second n-metal gate and the second n-metal gate includes a second bottom barrier metal layer, the n type work function metal layer, and a third p type work function metal layer sandwiched between the second bottom barrier metal layer and the n type work function metal layer. The third p type work function metal layer of the second nFET device and the third bottom barrier metal layer of the first nFET device include a same material.

Abstract translation: 具有金属栅极的半导体器件包括衬底，其上形成的第一nFET器件和形成在其上的第二nFET器件。 第一nFET器件包括第一n型金属栅极，并且第一n型金属栅极包括第三底部阻挡金属层和n型功函数金属层。 n型功函数金属层直接接触第三底层阻挡层。 第二nFET器件包括第二n型金属栅极，第二n型金属栅极包括第二底部阻挡金属层，n型功函数金属层和夹在第二底部阻挡金属之间的第三p型功函数金属层 层和n型功函数金属层。 第二nFET器件的第三p型功函数金属层和第一nFET器件的第三底阻挡金属层包括相同的材料。

公开(公告)号：US20160315171A1

公开(公告)日：2016-10-27

申请号：US14727853

申请日：2015-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Jun-Jie Wang ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Hung-Chan Lin ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653

Abstract: A method for manufacturing a semiconductor device having a metal gate includes forming a filling layer and a high-K gate dielectric layer in the first recess between a pair of spacers, wherein the high-K gate dielectric layer and the filling layer are stacked in the first recess sequentially, and an exposed top surface of the high-K gate dielectric layer and a top surface of the filling layer are lower than a top surface of each spacer; and removing a part of each spacer and widening the first recess on the top surface of the filling layer to form a second recess, wherein a width of the second recess is larger than a width of the first recess.

Abstract translation: 一种具有金属栅极的半导体器件的制造方法包括在一对间隔物之间​​的第一凹部中形成填充层和高K栅极电介质层，其中高K栅极介电层和填充层堆叠在 第一凹部，高K栅极电介质层的露出顶表面和填充层的顶表面比每个间隔物的顶表面低; 并且移除每个间隔物的一部分并加宽填充层的顶表面上的第一凹部以形成第二凹部，其中第二凹部的宽度大于第一凹部的宽度。

公开(公告)号：US20160300942A1

公开(公告)日：2016-10-13

申请号：US14703904

申请日：2015-05-05

Applicant: United Microelectronics Corp.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Jyh-Shyang Jenq

IPC: H01L29/78 ,  H01L21/324 ,  H01L21/02 ,  H01L29/167 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/66803

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure thereon; forming a spacer adjacent to the first fin-shaped structure; using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, in which the second fin-shaped structure comprises a top portion and a bottom portion; and forming a doped portion in the bottom portion of the second fin-shaped structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有第一鳍状结构的基底; 形成邻近所述第一鳍状结构的间隔件; 使用间隔件作为掩模来去除用于形成第二鳍状结构的基板的一部分，其中第二鳍状结构包括顶部和底部; 以及在所述第二鳍状结构的底部中形成掺杂部分。