公开(公告)号：US20200381408A1

公开(公告)日：2020-12-03

申请号：US16996356

申请日：2020-08-18

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu ,  Li Hong Xiao

IPC: H01L25/10 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L27/11573 ,  H01L27/11582

Abstract: Embodiments of three-dimensional (3D) memory devices with stacked device chips using interposers and fabrication methods thereof are disclosed. In an example, a method for forming a 3D memory device is disclosed. An alternating conductor/dielectric stack is formed at a first side of a chip substrate. A memory string extending vertically through the alternating conductor/dielectric stack is formed. A chip contact is formed at a second side opposite to the first side of the chip substrate and is electrically connected to the memory string. A first interposer contact is formed at a first side of an interposer substrate. A second interposer contact is formed at a second side opposite to the first side of the interposer substrate and is electrically connected to the first interposer contact through the interposer substrate. The first interposer contact is attached to the chip contact.

公开(公告)号：US20200350321A1

公开(公告)日：2020-11-05

申请号：US16727893

申请日：2019-12-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Weihua Cheng ,  Jun Liu

IPC: H01L27/11 ,  H01L21/76 ,  H01L23/00

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

公开(公告)号：US20200328176A1

公开(公告)日：2020-10-15

申请号：US16727889

申请日：2019-12-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L23/00 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/108 ,  H01L27/11

Abstract: Embodiments of three-dimensional (3D) memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes NAND memory cells and a first bonding layer including first bonding contacts. The 3D memory device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The 3D memory device also includes a third semiconductor structure including SRAM cells, a third bonding layer including third bonding contacts, and a fourth bonding layer including fourth bonding contacts. The third and fourth bonding layers are on both sides of the SRAM cells. The semiconductor device further includes a first bonding interface between the first and third bonding layers. The first bonding contacts are in contact with the third bonding contacts at the first bonding interface. The 3D memory device further includes a second bonding interface between the second and fourth bonding layers. The second bonding contacts are in contact with the fourth bonding contacts at the second bonding interface.

公开(公告)号：US10510415B1

公开(公告)日：2019-12-17

申请号：US16165660

申请日：2018-10-19

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Zongliang Huo ,  Jun Liu ,  Zhiliang Xia ,  Li Hong Xiao

IPC: G11C16/08 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L29/792

Abstract: A memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first substrate and one or more peripheral devices on the first substrate. The second semiconductor structure includes a first set of conductive lines electrically coupled with a first set of a plurality of vertical structures and a second set of conductive lines electrically coupled with a second set of the plurality of vertical structures different from the first set of the plurality of vertical structures. The first set of conductive lines are vertically distanced from one end of the plurality of vertical structures and the second set of conductive lines are vertically distanced from an opposite end of the plurality of vertical structures.

公开(公告)号：US11950399B2

公开(公告)日：2024-04-02

申请号：US17524478

申请日：2021-11-11

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/822 ,  H01L25/065 ,  H10B12/00

CPC classification number: H10B10/12 ,  H01L21/02013 ,  H01L21/2007 ,  H01L21/8221 ,  H01L25/0657 ,  H10B12/09

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a device layer, a first interconnect layer, and a first bonding layer. The device layer includes a processor and a logic circuit, and the first bonding layer includes a first bonding contact. The semiconductor device also includes a second semiconductor structure including an array of static random-access memory (SRAM) cells, a second interconnect layer, and a second bonding layer including a second bonding contact. The first bonding contact is in contact with the second bonding contact. The processor is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer. The logic circuit is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer.

公开(公告)号：US11910602B2

公开(公告)日：2024-02-20

申请号：US17144562

申请日：2021-01-08

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Jun Liu ,  Zongliang Huo

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/225 ,  H01L21/306 ,  H01L21/311 ,  H01L29/10 ,  H10B43/35 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/321

CPC classification number: H10B43/27 ,  H01L21/02178 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2251 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/1037 ,  H10B43/35 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/40117

Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

公开(公告)号：US11721668B2

公开(公告)日：2023-08-08

申请号：US16727890

申请日：2019-12-26

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu ,  Weihua Cheng

IPC: H01L25/065 ,  H01L25/18 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/78 ,  H01L24/08 ,  H01L24/80 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure including a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including a plurality of first bonding contacts. The semiconductor device also includes a second semiconductor structure including an array of dynamic random-access memory (DRAM) cells and a second bonding layer including a plurality of second bonding contacts. The semiconductor device further includes a bonding interface between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

公开(公告)号：US11659702B2

公开(公告)日：2023-05-23

申请号：US17202200

申请日：2021-03-15

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/20 ,  H01L21/822 ,  H01L25/065 ,  H01L27/108

CPC classification number: H01L27/1104 ,  H01L21/02013 ,  H01L21/2007 ,  H01L21/8221 ,  H01L25/0657 ,  H01L27/10894

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of SRAM cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

公开(公告)号：US11631688B2

公开(公告)日：2023-04-18

申请号：US17540224

申请日：2021-12-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Jun Liu ,  Weihua Cheng

IPC: H01L27/11 ,  H01L27/1157 ,  H01L21/50 ,  H01L23/00 ,  H01L27/06 ,  H01L27/108 ,  H01L27/11578 ,  G11C14/00 ,  G11C16/04 ,  H01L25/18 ,  H01L25/00 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L21/02 ,  H01L21/20 ,  H01L21/76 ,  H01L21/822 ,  H01L25/065

Abstract: Embodiments of bonded unified semiconductor chips and fabrication and operation methods thereof are disclosed. In an example, a method for forming a unified semiconductor chip is disclosed. A first semiconductor structure is formed. The first semiconductor structure includes one or more processors, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

公开(公告)号：US11600636B2

公开(公告)日：2023-03-07

申请号：US17112448

申请日：2020-12-04

Applicant: Yangtze Memory Technologies Co., Ltd.

Inventor： Jun Liu ,  Zongliang Huo

IPC: H01L27/11582 ,  H01L21/02 ,  H01L21/225 ,  H01L21/306 ,  H01L21/311 ,  H01L27/1157 ,  H01L29/10 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/321

Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.