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公开(公告)号：US08875390B2
公开(公告)日：2014-11-04
申请号：US13663274
申请日：2012-10-29
Applicant: Kinsus Interconnect Technology Corp.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H01K3/00
CPC classification number: H05K3/4682 , H05K1/0271 , H05K2201/09136 , H05K2201/2018 , H05K2203/0152 , H05K2203/0376 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/4916
Abstract: A method of manufacturing a laminate circuit board which includes the sequential steps of metalizing the substrate to form the base layer, forming the first circuit metal layer, forming at least one insulation layer and at least one second circuit metal layer interleaved, removing the substrate, forming the support frame and forming the solder resist is disclosed. The laminate circuit board has a thickness less than 150 μm. The support frame which does not overlap the first circuit metal layer is formed on the edge of the base layer by the pattern transfer process after the substrate is removed. The base layer formed of at least one metal layer is not completely removed. The support frame provides enhanced physical support for the entire laminate circuit board without influence on the electrical connection of the circuit in the second circuit metal layer, thereby solving the warping problem.
Abstract translation: 一种叠层电路板的制造方法，其特征在于，包括使所述基板金属化以形成所述基底层的顺序步骤，形成所述第一电路金属层，形成至少一个绝缘层和交替插入的至少一个第二电路金属层，去除所述基板， 公开了形成支撑框架并形成阻焊剂的方法。 层叠电路板的厚度小于150μm。 在去除衬底之后，通过图案转印工艺在基层的边缘上形成不与第一电路金属层重叠的支撑框架。 由至少一个金属层形成的基底层没有被完全去除。 支撑框架对整个层叠电路板提供增强的物理支撑，而不影响第二电路金属层中的电路的电连接，从而解决翘曲问题。
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公开(公告)号：US20140290057A1
公开(公告)日：2014-10-02
申请号：US13853325
申请日：2013-03-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H05K3/46
CPC classification number: H05K3/4647 , H05K3/4038 , H05K2203/025 , H05K2203/063 , Y10T29/49155
Abstract: Disclosed is a method of manufacturing a stacked multilayer structure, including the steps of forming a first circuit layer with bumps on a substrate, punching an aluminum plate to form recesses corresponding to the bumps, forming openings in a plastic film including a glass fiber layer corresponding to the bumps, pressing the aluminum plate, the plastic film and the substrate, removing the aluminum plate, polishing to level the resulting surface, forming a second circuit layer connected to the first circuit layer, and finally removing the substrate to form the stacked multilayer structure. Because the glass fiber layer in the plastic film is not exposed after polishing, the thickness of the dielectric layer is uniform and the reliability of the circuit layer is improved so as to increase the yield.
Abstract translation: 公开了一种制造堆叠多层结构的方法，包括以下步骤：在基板上形成具有凸块的第一电路层，冲压铝板以形成与凸块相对应的凹部，在包括玻璃纤维层的塑料膜中形成开口 对铝合金板，塑料薄膜和基板进行压制，去除铝板，进行抛光以使所得表面平坦化，形成连接到第一电路层的第二电路层，最后移除基板以形成叠层多层 结构体。 由于塑料膜中的玻璃纤维层在研磨后不露出，所以介电层的厚度均匀，电路层的可靠性得以提高，从而提高产率。
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公开(公告)号：US08766102B2
公开(公告)日：2014-07-01
申请号：US13663303
申请日：2012-10-29
Applicant: Kinsus Interconnect Technology Corp.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
CPC classification number: H05K1/056 , H01L21/4857 , H01L21/486 , H01L23/13 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L2924/0002 , H05K1/0204 , H05K2201/029 , H05K2201/0323 , H05K2201/09054 , H05K2203/0323 , H05K2203/0384 , H05K2203/063 , H01L2924/00
Abstract: A chip support board structure which includes at least a metal substrate, a block layer, a paddle, an insulation layer, a circuit layer and a solder resist is disclosed. The circuit layer connects with the paddle. The material of the block layer is different from that of the metal substrate and the block layer is provided between the metal substrate and the paddle such that the shape and the depth of the paddle is maintained constant and the problem of different depth and easily peeling off is avoided, thereby improving the yield rate of the chip support board.
Abstract translation: 公开了至少包括金属基板，阻挡层，桨，绝缘层，电路层和阻焊剂的芯片支撑板结构。 电路层与桨连接。 阻挡层的材料与金属基板的材料不同，并且在金属基板和板之间设置阻挡层，使得桨的形状和深度保持恒定，并且具有不同深度并容易剥离的问题 从而提高了芯片支撑板的成品率。
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公开(公告)号：US20140116757A1
公开(公告)日：2014-05-01
申请号：US13663303
申请日：2012-10-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H05K1/05
CPC classification number: H05K1/056 , H01L21/4857 , H01L21/486 , H01L23/13 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L2924/0002 , H05K1/0204 , H05K2201/029 , H05K2201/0323 , H05K2201/09054 , H05K2203/0323 , H05K2203/0384 , H05K2203/063 , H01L2924/00
Abstract: A chip support board structure which includes at least a metal substrate, a block layer, a paddle, an insulation layer, a circuit layer and a solder resist is disclosed. The circuit layer connects with the paddle. The material of the block layer is different from that of the metal substrate and the block layer is provided between the metal substrate and the paddle such that the shape and the depth of the paddle is maintained constant and the problem of different depth and easily peeling off is avoided, thereby improving the yield rate of the chip support board.
Abstract translation: 公开了至少包括金属基板，阻挡层，桨，绝缘层，电路层和阻焊剂的芯片支撑板结构。 电路层与桨连接。 阻挡层的材料与金属基板的材料不同，并且在金属基板和板之间设置阻挡层，使得桨的形状和深度保持恒定，并且具有不同深度并容易剥离的问题 从而提高了芯片支撑板的成品率。
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公开(公告)号：US20140115889A1
公开(公告)日：2014-05-01
申请号：US13663274
申请日：2012-10-29
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Yu-Te Lu , De-Hao Lu
IPC: H05K3/10
CPC classification number: H05K3/4682 , H05K1/0271 , H05K2201/09136 , H05K2201/2018 , H05K2203/0152 , H05K2203/0376 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/4916
Abstract: A method of manufacturing a laminate circuit board which includes the sequential steps of metalizing the substrate to form the base layer, forming the first circuit metal layer, forming at least one insulation layer and at least one second circuit metal layer interleaved, removing the substrate, forming the support frame and forming the solder resist is disclosed. The laminate circuit board has a thickness less than 150 μm. The support frame which does not overlap the first circuit metal layer is formed on the edge of the base layer by the pattern transfer process after the substrate is removed. The base layer formed of at least one metal layer is not completely removed. The support frame provides enhanced physical support for the entire laminate circuit board without influence on the electrical connection of the circuit in the second circuit metal layer, thereby solving the warping problem.
Abstract translation: 一种叠层电路板的制造方法，其特征在于，包括使所述基板金属化以形成所述基底层的顺序步骤，形成所述第一电路金属层，形成至少一个绝缘层和交替插入的至少一个第二电路金属层，去除所述基板， 公开了形成支撑框架并形成阻焊剂的方法。 层叠电路板的厚度小于150μm。 在去除衬底之后，通过图案转印工艺在基层的边缘上形成不与第一电路金属层重叠的支撑框架。 由至少一个金属层形成的基底层没有被完全去除。 支撑框架对整个层叠电路板提供增强的物理支撑，而不影响第二电路金属层中的电路的电连接，从而解决翘曲问题。
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Patent Agency Ranking
66.发明授权Method for fabricating an interlayer conducting structure of an embedded circuitry 有权一种用于制造嵌入式电路的层间导电结构的方法公开(公告)号：US08161639B2
公开(公告)日：2012-04-24
申请号：US12895824
申请日：2010-09-30
Applicant: Chien-Wei Chang , Ting-Hao Lin , Yu-Te Lu
Inventor： Chien-Wei Chang , Ting-Hao Lin , Yu-Te Lu
IPC: H01K3/10
CPC classification number: H05K3/4679 , H05K1/0269 , H05K3/0035 , H05K3/421 , H05K3/4658 , H05K2201/09918 , Y10T29/49124 , Y10T29/49126 , Y10T29/4913 , Y10T29/49131 , Y10T29/49155 , Y10T29/49165
Abstract: A method for fabricating an interlayer conducting structure of an embedded circuitry is disclosed. In accordance with the method for fabricating an interlayer conducting structure of an embedded circuitry of the present invention, there is no laser conformal mask formed prior to laminating the first and second lamination plates. Instead, after the first and second lamination plates are laminated, a laser boring process is directly conducted to form a via hole. In such a way, even when there is an offset between the first and the second lamination plates in alignment, the risk of short circuit between different layers of lamination plates can be lowered without improving an interlayer offset value.
Abstract translation: 公开了一种用于制造嵌入式电路的层间导电结构的方法。 根据本发明的嵌入式电路的层间导电结构的制造方法，在层叠第一和第二层压板之前不形成激光共形掩模。 相反，在第一和第二层压板层压之后，直接进行激光钻孔工艺以形成通孔。 以这种方式，即使在第一和第二层压板之间存在偏移对准的情况下，也可以在不改善层间偏移值的情况下降低层压板的不同层之间短路的风险。
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公开(公告)号：US08051558B2
公开(公告)日：2011-11-08
申请号：US12329584
申请日：2008-12-06
Applicant: Ting-Hao Lin , Chien-Wei Chang
Inventor： Ting-Hao Lin , Chien-Wei Chang
CPC classification number: H05K1/162 , H05K1/165 , H05K1/167 , H05K3/108 , H05K3/205 , H05K2201/09236 , H05K2201/09881 , Y10T29/49002 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49155
Abstract: A manufacturing method for mainly embedding the passive device structure in the printed circuit board is presented. In this structure, both the source electrode and the ground electrode of the passive device belong to the same level, and includes several source branches and several ground branches that are formed vertically on the inside of the dielectric layer of the circuit board which are connected, respectively, to avoid the conducting between the source electrode and the ground electrode during lamination. When it is in the form of the capacitor structure, through the use of the ultra-fine wiring technique, these source branches and ground branches are separated by a small gap between each other. Therefore, the side face area and quantities of the source branches and ground branches are both increased.
Abstract translation: 提出了一种主要将无源器件结构嵌入印刷电路板的制造方法。 在该结构中，无源器件的源电极和接地电极都属于同一水平，并且包括垂直形成在电路板的电介质层的内部上的数个源极分支和几个接地分支， 以避免在层压期间源电极和接地电极之间的导电。 当它是电容器结构的形式时，通过使用超细布线技术，这些源极分支和接地分支之间彼此间有很小的间隙。 因此，源分支和接地分支的侧面积和数量都增加。
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公开(公告)号：US07573721B2
公开(公告)日：2009-08-11
申请号：US11749752
申请日：2007-05-17
Applicant: Ting-Hao Lin , Chien-Wei Chang
Inventor： Ting-Hao Lin , Chien-Wei Chang
IPC: H05K1/16
CPC classification number: H05K1/162 , H05K1/165 , H05K1/167 , H05K3/108 , H05K3/205 , H05K2201/09236 , H05K2201/09881 , Y10T29/49002 , Y10T29/49117 , Y10T29/49124 , Y10T29/49128 , Y10T29/49155
Abstract: Embedded passive device structure and its manufacturing method for mainly embedding the passive device structure in the printed circuit board are presented. In this structure, both the source electrode and the ground electrode of the passive device belong to the same level, and includes several source branches and several ground branches that are formed vertically on the inside of the dielectric layer of the circuit board which are connected, respectively, to avoid the conducting between the source electrode and the ground electrode during lamination. When it is in the form of the capacitor structure, through the use of the ultra-fine wiring technique, these source branches and ground branches are separated by a small gap between each other. Therefore, the side face area and quantities of the source branches and ground branches are both increased.
Abstract translation: 介绍了嵌入式无源器件结构及其主要将无源器件结构嵌入印刷电路板的制造方法。 在该结构中，无源器件的源电极和接地电极都属于同一水平，并且包括垂直形成在电路板的电介质层的内部的多个源极分支和几个接地分支， 以避免在层压期间源电极和接地电极之间的导电。 当它是电容器结构的形式时，通过使用超细布线技术，这些源极分支和接地分支之间彼此间有很小的间隙。 因此，源分支和接地分支的侧面积和数量都增加。
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公开(公告)号：US10779405B2
公开(公告)日：2020-09-15
申请号：US16045236
申请日：2018-07-25
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Chiao-Cheng Chang , Yi-Nong Lin
Abstract: A landless multilayer circuit board includes a first substrate, a first circuit, at least one connecting pillar, a second substrate, and a second circuit. The second substrate is on the surface of the first substrate, covering the first circuit, and exposing at least one top of the at least one connecting pillar exposed out of a surface of the second substrate, wherein an area of a portion of the at least one connecting pillar that is exposed out of the surface of the second substrate is greater than an area of a portion of the at least one connecting pillar that is connected to the first circuit. The second circuit is on the surface of the second substrate and the at least one connecting pillar, and connected to the portion of the at least one connecting pillar that is exposed out of the surface of the second substrate.
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公开(公告)号：US10440837B2
公开(公告)日：2019-10-08
申请号：US15864754
申请日：2018-01-08
Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.
Inventor： Ting-Hao Lin , Chiao-Cheng Chang , Yi-Nong Lin
Abstract: A manufacturing method of a double layer circuit board comprises forming at least one connecting pillar on a first circuit, wherein the at least one connecting pillar comprises a first end, connected to the first circuit, and a second end, opposite to the first end; forming a substrate on the first circuit and the at least one connecting pillar; drilling the substrate to expose a portion of the second end of the at least one connecting pillar, wherein the other portion of the second end of the at least one connecting pillar is covered by the substrate; and forming a second circuit on the substrate and the portion of the second end of the at least one connecting pillar, wherein an area of the first end connected to the first circuit layer is greater than an area of the portion of the second end connected to the second circuit layer.
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