公开(公告)号：US20150370661A1

公开(公告)日：2015-12-24

申请号：US14310835

申请日：2014-06-20

Applicant: INTEL CORPORATION

Inventor： Robert C. Swanson ,  Robert W. Cone ,  Malay Trivedi

IPC: G06F11/20 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F11/2033 ,  G06F11/1428 ,  G06F11/2002 ,  G06F13/4027 ,  G06F13/4221 ,  G06F2201/845 ,  G06F2201/85

Abstract: Method and apparatus for dynamic Node healing in a Multi-Node environment. A multi-node platform controller hub (MN-PCH) is configured to support multiple nodes through use of dedicated interfaces and components and shared capabilities. Interfaces and components may be configured to be used by respective nodes, or may be configured to support enhanced resiliency as redundant primary and spare interfaces and components. In response to detecting a failing or failing primary interface or component, the MN-PCH automatically performs failover operations to replace the primary with the spare. Moreover, the failover operation is transparent to the operating systems running on the platform's nodes.

Abstract translation: 多节点环境中动态节点愈合的方法和装置。 多节点平台控制器集线器（MN-PCH）被配置为通过使用专用接口和组件以及共享功能来支持多个节点。 接口和组件可以被配置为由相应节点使用，或者可以被配置为支持作为冗余主要和备用接口和组件的增强的弹性。 为了响应检测到故障或故障的主接口或组件，MN-PCH自动执行故障切换操作，以将备用主机替换为备用。 此外，故障切换操作对于在平台节点上运行的操作系统是透明的。

公开(公告)号：US08984335B2

公开(公告)日：2015-03-17

申请号：US13836391

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Sreekala Anandavally ,  Anand Haridass ,  Gerard M. Salem ,  Diyanesh B. C. Vidyapoornachary

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0724 ,  G06F11/079 ,  G06F11/1428 ,  G06F11/16 ,  G06F11/2028 ,  G06F11/2041

Abstract: Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.

Abstract translation: 本公开的实施例涉及一种装置，其包括易受错误状况影响的第一核心，以及第二核心，被配置为对第一核心执行诊断以识别错误状况的原因以及纠正错误状况的动作 命令恢复第一核心。

公开(公告)号：US08966161B2

公开(公告)日：2015-02-24

申请号：US13632161

申请日：2012-10-01

Applicant: Phison Electronics Corp.

Inventor： Te-Change Tsui ,  Tzung-Lin Wu

IPC: G06F12/16

CPC classification number: G06F11/1666 ,  G06F11/1428

Abstract: A memory storage device and a repairing method thereof are provided. The memory storage device has a rewritable non-volatile memory module having multiple physical units. The physical units include at least one backup physical unit which is configured to be accessed only by a specific command set and stored with at least one customized data. The method includes receiving a specific read command from a host system for reading the backup physical unit and transmitting the customized data therein to the host system when the memory storage device is capable of receiving and processing commands from the host system, the specific read command belongs to the specific command set; and writing the customized data from the host system into a corresponding physical unit to restore the memory storage device to a factory setting when receiving the writing command from the host system for writing the customized data.

Abstract translation: 提供了一种存储器存储装置及其修复方法。 存储器存储设备具有具有多个物理单元的可重写非易失性存储器模块。 物理单元包括至少一个备份物理单元，其被配置为仅由特定命令集访问并且与至少一个定制数据一起存储。 该方法包括当存储器存储设备能够接收和处理来自主机系统的命令时，从主机系统接收用于读取备份物理单元并将其中的定制数据发送到主机系统的特定读命令，该特定读命令属于 到具体的命令集; 以及当从主机系统接收到用于写入定制数据的写入命令时，将定制数据从主机系统写入相应的物理单元以将存储器存储设备恢复到出厂设置。

公开(公告)号：US08717882B2

公开(公告)日：2014-05-06

申请号：US13175798

申请日：2011-07-01

Applicant: Venkatraman Iyer ,  Robert G. Blankenship ,  Allen J. Baum

Inventor： Venkatraman Iyer ,  Robert G. Blankenship ,  Allen J. Baum

IPC: H04J3/06

CPC classification number: G06F11/1428 ,  G06F11/1423 ,  G06F11/1604

Abstract: Methods and apparatus relating to repurposing a data lane as a clock lane by migrating to reduced speed link operation are described. In one embodiment, speed of a link is reduced upon detection of failure on a clock lane of the link and one of a plurality of data lanes of a link is repurposed as a replacement clock lane. Other embodiments are also disclosed and claimed.

Abstract translation: 描述通过迁移到降低速度链接操作将与数据通道重新设置为时钟通道有关的方法和装置。 在一个实施例中，在检测到链路的时钟通道上的故障并且链路的多个数据通道中的一个被重新利用作为替换时钟通道时，链路的速度被降低。 还公开并要求保护其他实施例。

公开(公告)号：US20140108859A1

公开(公告)日：2014-04-17

申请号：US13836391

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Sreekala Anandavally ,  Anand Haridass ,  Gerard M. Salem ,  Diyanesh B.C. Vidyapoornachary

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0724 ,  G06F11/079 ,  G06F11/1428 ,  G06F11/16 ,  G06F11/2028 ,  G06F11/2041

Abstract: Embodiments of the disclosure are directed to an apparatus that comprises a first core susceptible to an error condition, and a second core configured to perform a diagnostic on the first core to identify a cause of the error condition and an action to remedy the error condition in order to recover the first core.

公开(公告)号：US20130275806A1

公开(公告)日：2013-10-17

申请号：US13785103

申请日：2013-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fadi Y. Busaba ,  Steven R. Carlough ,  Christopher A. Krygowski ,  Brian R. Prasky ,  Chung-Lung K. Shum

IPC: G06F11/14

CPC classification number: G06F11/1446 ,  G06F1/3287 ,  G06F11/0772 ,  G06F11/0781 ,  G06F11/0793 ,  G06F11/1407 ,  G06F11/1425 ,  G06F11/1428 ,  Y02D10/171

Abstract: A method for performing error recovery that includes creating, by a processor, a recovery checkpoint. The processor is dynamically switched into a non-recoverable processing mode of operation based on creating the software recovery checkpoint. The non-recoverable processing mode of operation is a mode in which a subset of hardware error recovery resources are powered-down or re-purposed for instruction processing. It is determined, during the non-recoverable processing mode of operation, that a new software recovery checkpoint is required. Based on the determining that a new software recovery checkpoint is required, the processor is dynamically switched into a recoverable processing mode of operation. The recoverable processing mode of operation is a mode in which hardware error recovery resources, including at least one of the hardware error recovery resources in the subset, are purposed for hardware error recovery operations.

Abstract translation: 一种用于执行错误恢复的方法，包括由处理器创建恢复检查点。 基于创建软件恢复检查点，处理器被动态切换到不可恢复的处理操作模式。 不可恢复的处理操作模式是硬件错误恢复资源的子集被掉电或重新用于指令处理的模式。 在不可恢复的处理操作模式下，确定需要新的软件恢复检查点。 基于确定需要新的软件恢复检查点，处理器被动态切换成可恢复的处理操作模式。 可恢复处理操作模式是硬件错误恢复资源（包括该子集中的至少一个硬件错误恢复资源）用于硬件错误恢复操作的模式。

公开(公告)号：US20130198737A1

公开(公告)日：2013-08-01

申请号：US13829157

申请日：2013-03-14

Applicant: Flextronics AP, LLC

Inventor： Christopher P. Ricci

IPC: G06F9/445

CPC classification number: G06F8/61 ,  B60Q11/00 ,  B60R25/01 ,  B60W50/00 ,  G06F11/0796 ,  G06F11/1428 ,  G06F11/2035 ,  G06F11/2041 ,  G06F11/3006 ,  G06F11/3051 ,  G06F11/3055 ,  G06F11/3409 ,  G06F11/349 ,  G06F13/10 ,  G06F13/14 ,  H04L12/40 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: The present disclosure describes a microprocessor executable installation supervisor operable to determine, for a selected computational component to be installed in the vehicle, whether the selected computational component satisfies a requirement and/or restriction associated with the selected computational component, when installed, and, when the selected computational component can satisfy the requirement and/or restriction, create a set of data structures in the selected computational component and/or a computer readable medium on board the vehicle to bind the selected computational component to the vehicle.

公开(公告)号：US08429663B2

公开(公告)日：2013-04-23

申请号：US12529367

申请日：2008-02-05

Applicant: Masamichi Takagi ,  Masayuki Mizuno ,  Hiroaki Inoue

Inventor： Masamichi Takagi ,  Masayuki Mizuno ,  Hiroaki Inoue

IPC: G06F9/50

CPC classification number: G06F9/5027 ,  G06F11/1428 ,  G06F11/3419 ,  G06F11/3433 ,  G06F2209/483 ,  G06F2209/501

Abstract: Even if a multiprocessor includes an uneven performance core, an inoperative core or a core that does not satisfy such a performance as designed but if the contrivance of task allocation can satisfy the requirement of an application to be executed, the multiple processors are shipped. In a task group allocation method for allocating, to a processor having a plurality of cores, task groups included in an application for the processor to execute, a calculation section measures performances and disposition patterns of the cores, generates a restricting condition associating the measured performances and disposition patterns of the cores with information indicating whether the application can be executed, and, with reference to the restricting condition, reallocates to the cores, the task groups that have previously been allocated to the cores.

Abstract translation: 即使多处理器包括不均衡的性能核心，不能满足设计性能的不工作核心或核心，但是如果任务分配的设计能够满足执行应用程序的要求，则会发送多个处理器。 在用于将具有多个核心的处理器分配给应用程序中的处理器执行的任务组的任务组分配方法中，计算部分测量核心的性能和配置模式，产生将测量性能 以及具有指示是否可以执行应用的信息的核心的配置模式，并且参考限制条件将已经分配给核心的任务组重新分配给核心。

公开(公告)号：US20120173922A1

公开(公告)日：2012-07-05

申请号：US13309598

申请日：2011-12-02

Applicant: Yao-Chun Cheng ,  Yuan-Ning Lien ,  Chuan Yung Liu ,  Feng-I Liu ,  Kuei Huang Liu ,  Michael J. Peters

Inventor： Yao-Chun Cheng ,  Yuan-Ning Lien ,  Chuan Yung Liu ,  Feng-I Liu ,  Kuei Huang Liu ,  Michael J. Peters

IPC: G06F11/14

CPC classification number: G06F11/1417 ,  G06F11/1428 ,  G06F11/2025 ,  G06F11/2038 ,  G06F11/2043

Abstract: An apparatus for handling a failed processor of a multiprocessor system including at least two processors interconnected by processor interconnects for facilitating transactions of the processors. The at least two processors include a first processor set as a default boot processor in response to a boot up operation of the multiprocessor computer, and a second processor. The apparatus includes: a baseboard management module for detecting and receiving health information of the processors; a multiplexer coupled to the baseboard management module and respectively to the processors, the multiplexer being operative to switch between the processors; and a processor ID controller coupled to the baseboard management module and respectively to the processors. In response to the health information indicating the first processor has failed, the processor ID controller sets the second processor as the default boot processor and the baseboard management module enables the multiplexer to switch to the second processor.

Abstract translation: 一种用于处理多处理器系统的故障处理器的装置，包括由处理器互连互连的至少两个处理器，以便于处理器的事务处理。 至少两个处理器包括响应于多处理器计算机的引导操作的第一处理器集合作为默认引导处理器，以及第二处理器。 该装置包括：用于检测和接收处理器的健康信息的基板管理模块; 耦合到所述基板管理模块并分别耦合到所述处理器的多路复用器，所述多路复用器可操作以在所述处理器之间切换; 以及耦合到所述基板管理模块并分别耦合到所述处理器的处理器ID控制器。 响应于指示第一处理器失败的健康信息，处理器ID控制器将第二处理器设置为默认引导处理器，并且基板管理模块使多路复用器切换到第二处理器。

公开(公告)号：US20120131288A1

公开(公告)日：2012-05-24

申请号：US13216212

申请日：2011-08-23

Applicant: Brian A. Box ,  John M. Rudosky ,  Stephen L. Wasson ,  Steven Hennick Kelem

Inventor： Brian A. Box ,  John M. Rudosky ,  Stephen L. Wasson ,  Steven Hennick Kelem

IPC: G06F12/00

CPC classification number: G06F12/0646 ,  G06F9/3897 ,  G06F11/1423 ,  G06F11/1428 ,  G06F15/7867 ,  H03K19/007 ,  H03K19/17752 ,  H03K19/17756

Abstract: The exemplary embodiments provide a reconfigurable integrated circuit capable of on-chip configuration and reconfiguration, comprising: a plurality of configurable composite circuit elements; a configuration and control bus; a memory; and a sequential processor. Each composite circuit element comprises: a configurable circuit; and an element interface and control circuit, the element interface and control circuit comprising an element controller and at least one configuration and control register to store one or more configuration and control words. The configuration and control bus is coupled to the plurality of configurable composite circuit elements, and comprises a plurality of address and control lines and a plurality of data lines. The sequential processor can write configurations to the configuration and control registers of an addressed configurable composite circuit element to configure or reconfigure the configurable circuit.

Abstract translation: 示例性实施例提供能够进行片上配置和重新配置的可重构集成电路，包括：多个可配置复合电路元件; 配置和控制总线; 记忆 和顺序处理器。 每个复合电路元件包括：可配置电路; 元件接口和控制电路，所述元件接口和控制电路包括元件控制器和至少一个配置和控制寄存器，用于存储一个或多个配置和控制字。 配置和控制总线耦合到多个可配置复合电路元件，并且包括多个地址和控制线以及多条数据线。 顺序处理器可以将配置写入寻址的可配置复合电路元件的配置和控制寄存器，以配置或重新配置可配置电路。