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    Sense amplifier with zero power idle mode
    61.
    发明授权
    Sense amplifier with zero power idle mode 失效
    具有零功率空闲模式的感应放大器

    公开(公告)号：US5963496A

    公开(公告)日：1999-10-05

    申请号：US64811

    申请日：1998-04-22

    Applicant: Saroj Pathak ,  Glen A. Rosendale ,  James E. Payne ,  Nianglamching Hangzo

    Inventor： Saroj Pathak ,  Glen A. Rosendale ,  James E. Payne ,  Nianglamching Hangzo

    IPC: G11C16/06 ,  G11C7/06 ,  G11C7/10 ,  G11C7/00

    CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C7/1036

    Abstract: A sense amplifier for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controller manner, in response to a control pulse. The control pulse is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps are utilized to read out in parallel fashion the N memory cells (bits) that constitute an accessed memory location. The sense amps are therefore active only of a period of time sufficient to read out a memory cell.

    Abstract translation: 用于串行配置存储器的读出放大器包括响应于控制脉冲以控制器方式启用和禁用的多个级。 在外部提供的时钟信号的每第N个周期产生控制脉冲，该时钟用于计时表示存储器件的内容的比特流。 在优选实施例中，N个这样的感测放大器用于并行地读出构成访问的存储器位置的N个存储器单元（位）。 因此，感测放大器仅在足以读出存储器单元的一段时间内是有效的。

    Memory circuit accommodating both serial and random access, having a synchronous DRAM device for writing and reading data
    62.
    发明授权
    Memory circuit accommodating both serial and random access, having a synchronous DRAM device for writing and reading data 失效
    容纳串行和随机存取的存储电路，具有用于写入和读取数据的同步DRAM装置

    公开(公告)号：US5805518A

    公开(公告)日：1998-09-08

    申请号：US483618

    申请日：1995-06-07

    Applicant: Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

    Inventor： Masashi Hashimoto ,  Gene A. Frantz ,  John Victor Moravec ,  Jean-Pierre Dolait

    IPC: G11C7/10 ,  G11C8/02 ,  H04B7/185 ,  G11C8/00

    CPC classification number: G09G5/391 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1072 ,  G11C7/1075 ,  H04B7/18502

    Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and ouput data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).

    Abstract translation: 公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。 存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。 存储器电路（14）被串行和随机地访问。 地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。 地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

    Semiconductor memory
    64.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US4783768A

    公开(公告)日：1988-11-08

    申请号：US042367

    申请日：1987-04-24

    Applicant: Nobuyoshi Tanimura

    Inventor： Nobuyoshi Tanimura

    IPC: G11C11/401 ,  G11C7/10 ,  G11C8/04 ,  G11C8/00

    CPC classification number: G11C8/04 ,  G11C7/1036

    Abstract: A semiconductor memory is disclosed which comprises a memory array, an address counter designating the address of the memory array, a shift register to which the data signals read out from the memory array are preset, and a control circuit. When all the data preset to the shift register is shifted out to an external terminal, the control circuit updates the address counter. The data produced from the new address of the memory array is again preset to the shift register. The same operation is thereafter repeated, thereby producing serial data signals at the external terminal. The semiconductor memory having such a construction can read out continuous data signals without any need for external address signals.

    Abstract translation: 公开了一种半导体存储器，其包括存储器阵列，指定存储器阵列的地址的地址计数器，预先从存储器阵列读出的数据信号的移位寄存器和控制电路。 当预设到移位寄存器的所有数据被移出到外部端子时，控制电路更新地址计数器。 从存储器阵列的新地址产生的数据再次预设为移位寄存器。 然后重复相同的操作，从而在外部端子处产生串行数据信号。 具有这种结构的半导体存储器可以读出连续数据信号，而不需要外部地址信号。

    Memory device and method for controlling row hammer
    67.
    发明授权
    Memory device and method for controlling row hammer 有权

    公开(公告)号：US11961548B2

    公开(公告)日：2024-04-16

    申请号：US17871917

    申请日：2022-07-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ho-Youn Kim

    IPC: G11C11/406 ,  G11C7/10

    CPC classification number: G11C11/40615 ,  G11C7/1036 ,  G11C11/40622

    Abstract: A row hammer control method and a memory device are provided. The memory device monitors the row hammer address(es) having the number of accesses equal to or more than a predetermined number of times or having a higher number of accesses as compared with other access addresses during the first row hammer monitoring time frame and malicious row hammer address(es) accessed at random sampling time points during the second row hammer monitoring time frame and being the same as the row hammer address(es), notifies a memory controller of the malicious row hammer address(es) when the number of malicious row hammer addresses exceeds a threshold value, and causes a target refresh a memory cell row physically adjacent to a memory cell row corresponding to the malicious row hammer address(es) to be performed.

    BUFFER CONTROL OF MULTIPLE MEMORY BANKS
    69.
    发明公开
    BUFFER CONTROL OF MULTIPLE MEMORY BANKS 审中-公开

    公开(公告)号：US20240087624A1

    公开(公告)日：2024-03-14

    申请号：US18516143

    申请日：2023-11-21

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Shih-Lien Linus Lu

    IPC: G11C7/22 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C7/1036 ,  G11C7/1057 ,  G11C7/1084

    Abstract: Disclosed herein are related to operating a memory system including memory banks and buffers. Each buffer may perform a write process to write data to a corresponding memory bank. In one aspect, the memory system includes a buffer controller including a queue register, a first pointer register, a second pointer register, and a queue controller. In one aspect, the queue register includes entries, where each entry may store an address of a corresponding memory bank. The first pointer register may indicate a first entry storing an address of a memory bank, on which the write process is predicted to be completed next. The second pointer register may indicate a second entry to be updated. The queue controller may configure the queue register according to the first pointer register and the second pointer register, and configure one or more buffers to perform the write process, according to the entries.

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