公开(公告)号：US20170002479A1

公开(公告)日：2017-01-05

申请号：US15264525

申请日：2016-09-13

Applicant: Silicon Genesis Corporation

Inventor： Francois J. Henley

IPC: C30B29/06 ,  C01B33/02 ,  C30B33/00 ,  B28D5/04

CPC classification number: C30B29/06 ,  B28D5/045 ,  C01B33/02 ,  C30B33/00 ,  C30B33/06 ,  H01L21/0201 ,  H01L21/02027 ,  H01L31/1804

Abstract: A method for slicing a crystalline material ingot includes providing a crystalline material boule characterized by a cropped structure including a first end-face, a second end-face, and a length along an axis in a first crystallographic direction extending from the first end-face to the second end-face. The method also includes cutting the crystalline material boule substantially through a first crystallographic plane in parallel to the axis to separate the crystalline material boule into a first portion with a first surface and a second portion with a second surface. The first surface and the second surface are planar surfaces substantially along the first crystallographic plane. The method further includes exposing either the first surface of the first portion or the second surface of the second portion, and performing a layer transfer process to form a crystalline material sheet from either the first surface of the first portion or from the second surface of the second portion.

Abstract translation: 一种用于切割晶体材料锭的方法包括提供一种结晶材料棒，其特征在于包括第一端面，第二端面和沿着轴线的长度的裁剪结构，所述第一端面，第二端面和第一结晶方向上的长度从第一端面 到第二个端面。 该方法还包括基本上通过平行于轴线的第一晶体平面切割结晶材料棒，以将结晶材料原子坯分离成具有第一表面的第一部分和具有第二表面的第二部分。 第一表面和第二表面是基本上沿着第一结晶平面的平面。 该方法还包括暴露第一部分的第一表面或第二部分的第二表面，并且执行层转移过程以从第一部分的第一表面或第二部分的第二表面形成结晶材料片 第二部分。

公开(公告)号：US09249523B2

公开(公告)日：2016-02-02

申请号：US14039597

申请日：2013-09-27

Applicant: Seung Bum Rim

Inventor： Seung Bum Rim

IPC: C25F3/30 ,  C25F3/12 ,  H01L21/02 ,  H01L31/068 ,  H01L31/18 ,  C25F7/00

CPC classification number: C25F3/30 ,  C25F3/12 ,  C25F7/00 ,  H01L21/0201 ,  H01L21/0203 ,  H01L21/306 ,  H01L31/0682 ,  H01L31/1804 ,  H01L31/1892 ,  Y02E10/547 ,  Y02P70/521

Abstract: Forming a porous layer on a silicon substrate is disclosed. Forming the porous layer can include placing a silicon substrate in a first solution and conducting a first current through the silicon substrate. It can further include conducting a second current through the silicon substrate resulting in a porous layer on the silicon substrate.

Abstract translation: 公开了在硅衬底上形成多孔层。 形成多孔层可以包括将硅衬底放置在第一溶液中并且传导第一电流通过硅衬底。 它还可以包括通过硅衬底导通第二电流，导致硅衬底上的多孔层。

公开(公告)号：US09218954B2

公开(公告)日：2015-12-22

申请号：US13872821

申请日：2013-04-29

Applicant: Sinmat, Inc.

Inventor： Rajiv K. Singh ,  Arul Chakkaravarthi Arjunan

IPC: H01L21/00 ,  H01L21/02 ,  C30B25/18 ,  C30B29/36 ,  H01L21/306 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L21/0201 ,  C30B25/186 ,  C30B29/36 ,  H01L21/0237 ,  H01L21/02378 ,  H01L21/02389 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/30608 ,  H01L21/30617 ,  H01L21/30625 ,  H01L29/1608 ,  H01L29/2003

Abstract: A method for forming an epitaxial layer on a substrate surface having crystalline defect or amorphous regions and crystalline non-defect regions includes preferential polishing or etching the crystalline defect or amorphous regions relative to the crystalline non-defect regions to form a decorated substrate surface having surface recess regions. A capping layer is deposited on the decorated substrate surface to cover the crystalline non-defect regions and to at least partially fill the surface recess regions. The capping layer is patterned by removing the capping layer over the crystalline non-defect regions to form exposed non-defect regions while retaining the capping layer in at least a portion of the surface recess regions. Selective epitaxy is then used to form the epitaxial layer, wherein the capping layer in the surface recess regions restricts epitaxial growth of the epitaxial layer over the surface recess regions.

Abstract translation: 在具有晶体缺陷或非晶区域和晶体非缺陷区域的衬底表面上形成外延层的方法包括相对于晶体非缺陷区域优先抛光或蚀刻晶体缺陷或非晶区域，以形成具有表面的装饰衬底表面 凹陷区域。 覆盖层沉积在装饰的衬底表面上以覆盖晶体非缺陷区域并且至少部分地填充表面凹陷区域。 通过在晶体非缺陷区域上移除覆盖层来形成覆盖层，以形成暴露的非缺陷区域，同时将覆盖层保持在表面凹陷区域的至少一部分中。 然后使用选择性外延形成外延层，其中表面凹陷区域中的覆盖层限制外延层在表面凹陷区域上的外延生长。

公开(公告)号：US09117758B2

公开(公告)日：2015-08-25

申请号：US14495259

申请日：2014-09-24

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Keiji Ishibashi

IPC: H01L31/0312 ,  H01L21/304 ,  H01L21/02 ,  H01L29/16 ,  C30B29/36 ,  C30B33/00 ,  H01L21/28 ,  H01L29/34 ,  H01L29/36 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L21/304 ,  C30B23/025 ,  C30B29/36 ,  C30B33/00 ,  H01L21/02002 ,  H01L21/02008 ,  H01L21/0201 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02658 ,  H01L21/28 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/34 ,  H01L29/36 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813 ,  Y10T428/21

Abstract: A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation σ of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation σ of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.

Abstract translation: 提供了能够实现在形成外延膜或半导体元件的步骤中产生的缺陷概率低的衬底，包括衬底的半导体器件以及制造半导体器件的方法。 基板是具有前表面和背面的基板，其中前表面的至少一部分由单晶碳化硅构成，所述基板的前表面的表面粗糙度Ra的平均值不大于0.5 nm，标准偏差 的表面粗糙度Ra不大于0.2nm，背面的表面粗糙度Ra的平均值不小于0.3nm且不大于10nm，标准偏差＆sgr; 的表面粗糙度Ra不大于3nm，前表面直径D不小于110mm。

公开(公告)号：US20150228637A1

公开(公告)日：2015-08-13

申请号：US14696893

申请日：2015-04-27

Applicant: Dai Nippon Printing Co., Ltd.

Inventor： Tatsuro Takagaki

IPC: H01L27/02 ,  H01L21/02

CPC classification number: H01L27/0207 ,  B81B2201/0235 ,  B81B2203/0136 ,  B81B2207/053 ,  B81C1/00214 ,  G01P15/0802 ,  G01P15/123 ,  G01P15/125 ,  G01P15/18 ,  G01P2015/0814 ,  G01P2015/0842 ,  H01L21/0201 ,  H01L23/544 ,  H01L41/332 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A silicon wafer includes a plurality of chip patterns arranged parallel to a first direction and a second direction intersecting the first direction, wherein the plurality of chip patterns include one or more patterns arranged in the first direction and the second direction in a straight line, the plurality of chip patterns include a first chip pattern and a second chip pattern adjacent to the first chip pattern, and the second chip pattern is arranged by rotating the first chip pattern at 90 degrees, the plurality of chip patterns are arranged so that an axis in which a cleavage plane of the silicon wafer and a surface arranged with the pattern on the silicon wafer intersect, and the first direction are different, and an angle between the axis and the first direction of the second chip pattern is 90 degrees.

Abstract translation: 硅晶片包括平行于第一方向布置的多个芯片图案和与第一方向相交的第二方向，其中多个芯片图案包括沿第一方向布置的一个或多个图案，并且第二方向为直线， 多个芯片图案包括与第一芯片图案相邻的第一芯片图案和第二芯片图案，并且通过以90度旋转第一芯片图案来布置第二芯片图案，多个芯片图案被布置成使得 其中硅晶片的解理面和硅晶片上的图案布置的表面相交，第一方向不同，并且第二芯片图案的轴与第一方向之间的角度为90度。

公开(公告)号：US09076750B2

公开(公告)日：2015-07-07

申请号：US14005975

申请日：2012-04-03

Applicant: Michito Sato

Inventor： Michito Sato

IPC: H01L29/06 ,  H01L21/78 ,  H01L29/34 ,  H01L21/02

CPC classification number: H01L29/34 ,  H01L21/0201 ,  H01L21/02024

Abstract: A semiconductor wafer having sag formed at an outer periphery at the time of polishing, wherein a displacement of the semiconductor wafer in a thickness direction is 100 nm or less between a center and a outer peripheral sag start position of the semiconductor wafer, and the center of the semiconductor wafer has a convex shape, an amount of outer peripheral sag of the semiconductor wafer is 100 nm or less, and the outer peripheral sag start position is away from an outer peripheral portion of the semiconductor wafer toward the center or 20 mm or more away from an outer peripheral end of the semiconductor wafer toward the center, the outer peripheral portion being a measurement target of ESFQR.

Abstract translation: 在抛光时在外周形成有凹陷的半导体晶片，其中半导体晶片在厚度方向上的位移在半导体晶片的中心和外周起始位置之间为100nm以下，中心 半导体晶片的外周凹陷量为100nm以下，外周凹陷开始位置远离半导体晶片的外周部朝向中央或20mm，或者 更远离半导体晶片的外周端朝向中心，外周部​​是ESFQR的测量对象。

公开(公告)号：US20140363983A1

公开(公告)日：2014-12-11

申请号：US13912666

申请日：2013-06-07

Applicant: ASM IP Holding B.V.

Inventor： Akinori Nakano ,  Shintaro Ueda

IPC: H01L21/02

CPC classification number: H01L21/02112 ,  C23C16/02 ,  C23C16/401 ,  H01L21/0201 ,  H01L21/02115 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02277 ,  H01L21/76834 ,  H01L21/76837

Abstract: A method for filling recesses of a substrate with an insulation film includes: (i) exposing surfaces of the recesses of the substrate to a pre-deposition gas in a reactive state in a reaction space to treat the surfaces with reactive hydrocarbons generated from the pre-deposition gas without filling the recesses; and (ii) depositing a flowable insulation film using a process gas other than the pre-deposition gas on a surface of the substrate to fill the recesses treated in step (i) therewith by plasma reaction. The pre-deposition gas has at least one hydrocarbon unit in its molecule.

Abstract translation: 用绝缘膜填充基板的凹部的方法包括：（i）将基板的凹部的表面暴露于处于反应状态的反应性状态的预沉积气体，以便在由表面产生的活性烃 - 不填充凹槽的沉积气体; 和（ii）使用除了预沉积气体之外的处理气体在基板的表面上沉积可流动的绝缘膜，以通过等离子体反应填充步骤（i）中处理的凹部。 预沉积气体在其分子中具有至少一个烃单元。

公开(公告)号：US08872189B2

公开(公告)日：2014-10-28

申请号：US13564779

申请日：2012-08-02

Applicant: Keiji Ishibashi

Inventor： Keiji Ishibashi

IPC: H01L31/0312 ,  H01L21/00 ,  H01L21/20 ,  H01L21/36 ,  B32B3/02 ,  B24B1/00 ,  C30B29/36 ,  C30B33/00 ,  H01L21/02 ,  H01L29/16 ,  H01L29/04 ,  H01L29/66 ,  H01L29/45 ,  H01L29/78 ,  H01L29/36 ,  H01L29/34 ,  H01L29/49

CPC classification number: H01L21/304 ,  C30B23/025 ,  C30B29/36 ,  C30B33/00 ,  H01L21/02002 ,  H01L21/02008 ,  H01L21/0201 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02658 ,  H01L21/28 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/34 ,  H01L29/36 ,  H01L29/45 ,  H01L29/4966 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813 ,  Y10T428/21

Abstract: A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation σ of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation σ of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.

Abstract translation: 提供了能够实现在形成外延膜或半导体元件的步骤中产生的缺陷概率低的衬底，包括衬底的半导体器件以及制造半导体器件的方法。 基板是具有前表面和背面的基板，其中前表面的至少一部分由单晶碳化硅构成，所述基板的前表面的表面粗糙度Ra的平均值不大于0.5 nm，标准偏差 的表面粗糙度Ra不大于0.2nm，背面的表面粗糙度Ra的平均值不小于0.3nm且不大于10nm，标准偏差＆sgr; 的表面粗糙度Ra不大于3nm，前表面直径D不小于110mm。

公开(公告)号：US08835327B2

公开(公告)日：2014-09-16

申请号：US13747046

申请日：2013-01-22

Applicant: Fujitsu Semiconductor Limited

Inventor： Masanori Terahara ,  Hikaru Kokura ,  Akihiro Hasegawa ,  Atsuo Fushida ,  Fumihiko Akaboshi

IPC: H01L21/302

CPC classification number: H01L21/0201 ,  H01J37/321 ,  H01L21/32137 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/6831

Abstract: A method of manufacturing a semiconductor device disclosed herein includes: mounting a substrate on an electrostatic chuck placed inside a chamber, the electrostatic chuck having a first temperature and the substrate being retained in advance in an atmosphere having a second temperature lower than the first temperature; fixing the substrate onto the electrostatic chuck by applying a voltage to the electrostatic chuck; heating the electrostatic chuck to a third temperature higher than the first temperature and the second temperature after mounting the substrate; and processing the substrate after the heating.

Abstract translation: 制造本文公开的半导体器件的方法包括：将衬底安装在放置在室内的静电吸盘上，所述静电吸盘具有第一温度，并且所述衬底预先保持在具有低于第一温度的第二温度的气氛中; 通过向静电卡盘施加电压将基板固定到静电卡盘上; 在安装基板之后，将静电卡盘加热至高于第一温度和第二温度的第三温度; 并在加热之后处理基板。

公开(公告)号：US20140162433A1

公开(公告)日：2014-06-12

申请号：US14099032

申请日：2013-12-06

Applicant: Graphene Frontiers

Inventor： Bruce Ira Willner

IPC: H01L21/02 ,  H01L21/67

CPC classification number: B32B37/24 ,  B32B38/08 ,  B32B38/10 ,  B32B2037/243 ,  B32B2037/246 ,  C01B32/184 ,  C01B32/194 ,  H01L21/0201 ,  H01L21/67092 ,  H01L21/67132

Abstract: A method is disclosed which includes: forming at least one layer of material on at least part of a surface of a first substrate, wherein a first surface of the at least one layer of material is in contact with the first substrate thereby defining an interface; attaching a second substrate to a second surface of the at least one layer of material; forming bubbles at the interface; and applying mechanical force; whereby the second substrate and the at least one layer of material are jointly separated from the first substrate. Related arrangements are also described.

Abstract translation: 公开了一种方法，其包括：在第一衬底的表面的至少一部分上形成至少一层材料，其中所述至少一层材料的第一表面与所述第一衬底接触，从而限定界面; 将第二衬底附接到所述至少一层材料的第二表面; 在界面处形成气泡; 并施加机械力; 由此所述第二基板和所述至少一个材料层与所述第一基板共同分离。 还描述了相关的布置。