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公开(公告)号:US20190067415A1
公开(公告)日:2019-02-28
申请号:US15774286
申请日:2016-09-17
Inventor: Min REN , Yumeng ZHANG , Cong DI , Jingzhi XIONG , Zehong LI , Jinping ZHANG , Wei GAO , Bo ZHANG
CPC classification number: H01L29/0615 , H01L29/0638 , H01L29/407 , H01L29/7811 , H01L29/7813 , H01L29/7823
Abstract: A junction termination with an internal field plate, the field plate structure and the junction termination extension region are folded inside the device to make full use of the thickness of the drift region in the body, thereby reducing the area of the termination and relieving the electric field concentration at the end of the PN junction. The breakdown position is transferred from the surface into the body of the original PN junction, and the withstand voltage of termination can reach to the breakdown voltage of the parallel plane junction. Under such design, a smaller area can be obtained than that of the conventional structure at the same withstand voltage.
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公开(公告)号:US20190057831A1
公开(公告)日:2019-02-21
申请号:US16131028
申请日:2018-11-13
Inventor: Zhaoyun Duan , Xin Wang , Xirui Zhan , Fei Wang , Shifeng Li , Zhanliang Wang , Yubin Gong
Abstract: A left-handed material extended interaction klystron includes: an input cavity, a middle cavity, an output cavity, first-section drift tube and a second-section drift tube; wherein the input cavity, the middle cavity and the output cavity are all cylindrical resonant cavities having arrays of Complementary electric Split-Ring Resonator (CeSRR) unit cells provided therein; wherein a first side of the input cavity is an input channel of an electron beam, a second side connects the middle cavity via the first-section drift tube; a first T-shaped coaxial input structure is provided in the input cavity; a first side of the output cavity is for connecting a collector, a second side of the output cavity connects the middle cavity via the second-section drift tube, a second T-shaped coaxial output structure is provided in the output cavity.
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公开(公告)号:US20190036214A1
公开(公告)日:2019-01-31
申请号:US15959305
申请日:2018-04-23
Inventor: Yujian CHENG , Yichen ZHONG , Renbo HE , Yan LIU , Yong FAN , Kaijun SONG , Bo ZHANG , Xianqi LIN , Yonghong ZHANG
Abstract: An antenna for generating an arbitrarily directed Bessel beam, including a beam-forming plane and a feeding horn, the beam-forming plane is a dual-layer dielectric substrate structure having a beam focusing function, including: a printed circuit bottom layer, a high-frequency dielectric substrate lower layer, a printed circuit middle layer, a high-frequency dielectric substrate upper layer, and, a printed circuit upper layer; the printed circuit bottom layer, the high-frequency dielectric substrate lower layer, the printed circuit middle layer, the high-frequency dielectric substrate upper layer, and the printed circuit upper layer are co-axially stacked from the bottom to the top: the beam-forming plane is entirely divided into periodically arranged beam-forming units by a plurality of meshes, and each beam-forming unit consists of printed circuit upper, middle and lower metal patches of which centers are on the same longitudinal axis, the high-frequency dielectric substrate lower layer and the high-frequency dielectric substrate upper layer.
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74.
公开(公告)号:US20190021075A1
公开(公告)日:2019-01-17
申请号:US15836947
申请日:2017-12-11
Inventor: Xuesong TAN , Jieran WANG , Yifan WANG
CPC classification number: H04W72/044 , H04B1/40 , H04B1/713 , H04W72/0406
Abstract: This invention relates to the field of communication technology, and particularly to a communication exchange mechanism design based on frequency hopping, which is applicable to cognitive radio networks. A method for generating hopping frequency sequences for multi-transceiver cognitive radio networks is provided, so as to realize the optimization and tradeoff of the five performance parameters, i.e. DoR, MTTR, AITR, CL, and NSS. That, is, for a given DoR, the frequency-hopping system should minimize the NSS of the clock synchronous and asynchronous frequency-hopping systems under the condition of MTTR=ATTR=1 and CL
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75.
公开(公告)号:US10180899B2
公开(公告)日:2019-01-15
申请号:US15112689
申请日:2014-07-30
Inventor: Ting Chen , Xiaosong Zhang , Dong Wang , Ruidong Chen , Weina Niu , Xiaofen Wang
Abstract: A device and a method are provided to automatically generate test case for embedded software. This invention is in software test field, including symbolic execution kernel module, path selection module, solver, debugger, concrete execution kernel module and debugger agent module. The tested software and test cases are uploaded from the host system to the embedded system through debugger and debugger agent. The concrete execution kernel module starts the tested software. The symbolic execution kernel module captures the run-time information of the tested software through the debugger. When the tested software operates on the symbol source, the symbolic execution kernel module marks the symbol source, tracks the symbol propagation, generates path condition and sends the path condition to path selection module. This invention can automatically generate test cases for embedded software, which doesn't need the source code of the tested software and can be conveniently used for commercial software.
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公开(公告)号:US10175302B2
公开(公告)日:2019-01-08
申请号:US15586062
申请日:2017-05-03
Inventor: Qishui Zhong , Baihua Li , Hui Li , Yuqing Zhao
Abstract: Disclosed is a power system including a battery pack and a battery management system, the battery management system including a controller and a storage unit storing one or more executable programs executable to achieve battery functions.
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公开(公告)号:US10135426B1
公开(公告)日:2018-11-20
申请号:US15960580
申请日:2018-04-24
Applicant: University of Electronic Science and Technology of China , Institute of Electronic and Information Engineering of UESTC in Guangdong
IPC: H03K3/012 , H03K17/041 , H03K17/16
Abstract: A gate charge and discharge adjustment regulating circuit for a gate control device belongs to the power electronics technology field. The switch control signal is connected to the control terminals of the four analog switches. The gate control signal is loaded on the gate of the correct field effect transistor under the action of the four analog switches to control the switching-on degree so as to achieve the purpose of adjusting the gate driving signal current, that is, regulating the gate charge and discharge currents of the gate control device to realize the change of the switching characteristics and conduction characteristics. The switch control signal is connected to the input terminal of the gate driving module to control the gate driving module to generate the gate driving signal.
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78.
公开(公告)号:US20180252590A1
公开(公告)日:2018-09-06
申请号:US15968758
申请日:2018-05-02
Inventor: Ziji Liu , Shengchen Zhao , Zhiqing Liang , Hongbo Zhang , Tao Wang , Yadong Jiang
CPC classification number: G01J5/522 , G01J5/10 , G01J2005/0048 , G01R31/2656
Abstract: A system for testing thermal response time of an uncooled infrared focal plane detector array and a method therefor is provided. The system comprises: a blackbody, a chopper, a detector unit under test and a testing system. The method comprises: emitting radiation by the blackbody, chopping by the chopper, then radiating the radiation to the uncooled infrared focal plane detector array under test; generating different responses on the radiation at different chopping frequencies by the uncooled infrared focal plane detector array under test; collecting different response values of the uncooled infrared focal plane detector array under test at different chopping frequencies; obtaining response amplitude at a corresponding frequency in a frequency domain by FFT; fitting according to a formula Rv ( f ) = Rv ( 0 ) 1 + ( 2 π f τ ) 2 to obtain the thermal response time.
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公开(公告)号:US10068965B1
公开(公告)日:2018-09-04
申请号:US15718001
申请日:2017-09-28
Inventor: Ming Qiao , Yang Yu , Wentong Zhang , Zhengkang Wang , Zhenya Zhan , Bo Zhang
IPC: H01L29/06 , H01L29/78 , H01L27/02 , H01L29/40 , H01L29/739 , H01L29/735
Abstract: The present invention relates to a lateral high-voltage device. The device includes a dielectric trench region. A doping-overlapping structure with different doping types alternating mode is provided at least below, on a left side of, or on a right side of the dielectric trench region. The device also includes a dielectric layer, a body field plate, a polysilicon gate, a gate oxide layer, a first N-type heavy doping region, a second N-type heavy doping region, a P-type heavy doping region, a P-well region, the first N-type doping pillar, the second N-type doping pillar, the third N-type doping pillar, the first P-type doping pillar, and the second P-type doping pillar. The invention adopts a dielectric trench region in the drift region to keep the breakdown voltage BV of the device while reducing the surface area of the device, and effectively reducing the device's specific On-Resistance RON,sp.
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80.
公开(公告)号:US20180198457A1
公开(公告)日:2018-07-12
申请号:US15460219
申请日:2017-03-15
Inventor: Hua FAN , Hadi HEIDARI , Franco MALOBERTI , Dagang LI , Daqian HU , Yuanjun CEN
CPC classification number: H03M1/004 , H03M1/1009 , H03M1/38
Abstract: A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter by capacitor re-configuration, the method including: 1) arranging 128 unit capacitors in a positive array and a negative array, respectively, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; 2) acquiring 128 digital codes corresponding to 128 groups of capacitors; 3) sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained in 2), and recording the 128 groups of capacitors after sorting as C1-C128; and 4) selecting 64 groups of capacitors from C33 to C96, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter.
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