公开(公告)号：US08932802B2

公开(公告)日：2015-01-13

申请号：US13762446

申请日：2013-02-08

Applicant: Applied Materials, Inc.

Inventor： Banqiu Wu ,  Ajay Kumar ,  Omkaram Nalamasu

IPC: G03F7/26 ,  G03F7/16

CPC classification number: G03F7/16 ,  G03F7/0035 ,  G03F7/165 ,  G03F7/167

Abstract: Methods and apparatus for performing an atomic layer deposition lithography process are provided in the present disclosure. In one embodiment, a method for forming features on a material layer in a device includes pulsing a first reactant gas mixture to a surface of a substrate disposed in a processing chamber to form a first monolayer of a material layer on the substrate surface, directing an energetic radiation to treat a first region of the first monolayer, and pulsing a second reactant gas mixture to the substrate surface to selectively form a second monolayer on a second region of the first monolayer.

Abstract translation: 在本公开中提供了用于执行原子层沉积光刻工艺的方法和装置。 在一个实施例中，用于在器件中的材料层上形成特征的方法包括将第一反应气体混合物脉动到设置在处理室中的衬底的表面，以在衬底表面上形成材料层的第一单层， 高能辐射以处理第一单层的第一区域，以及将第二反应气体混合物脉冲至衬底表面以在第一单层的第二区域上选择性地形成第二单层。

公开(公告)号：US08846498B2

公开(公告)日：2014-09-30

申请号：US14148499

申请日：2014-01-06

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar

IPC: H01L21/00 ,  H01L21/78

CPC classification number: H01L21/78 ,  B23K26/0608 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  H01L21/3086

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a multi-step laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模。 掩模由覆盖和保护集成电路的层组成。 用多步骤激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模。 图案化使得集成电路之间的半导体晶片的区域露出。 然后通过图案化掩模中的间隙蚀刻半导体晶片，以对集成电路进行分离。

公开(公告)号：US08652940B2

公开(公告)日：2014-02-18

申请号：US13851442

申请日：2013-03-27

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Saravjeet Singh ,  Ajay Kumar

IPC: H01L21/00

CPC classification number: H01L21/78 ,  B23K26/0608 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/172 ,  H01L21/3086

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a multi-step laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract translation: 对具有多个集成电路的每个晶片进行切割的半导体晶片的方法进行了说明。 一种方法包括在半导体晶片上形成掩模。 掩模由覆盖和保护集成电路的层组成。 用多步骤激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模。 图案化使得集成电路之间的半导体晶片的区域露出。 然后通过图案化掩模中的间隙蚀刻半导体晶片，以对集成电路进行分离。