公开(公告)号：US20210035738A1

公开(公告)日：2021-02-04

申请号：US16306889

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Jiun Hann Sir ,  Min Suet Lim

IPC: H01G4/224 ,  H05K1/02 ,  H01G4/005 ,  H01L23/16 ,  H05K3/28 ,  H01L49/02

Abstract: Electronic device package stiffener and capacitor technology is disclosed. A combination stiffener and capacitor can include a structural material configured to be coupled to a substrate. The structural material can have a shape configured to provide mechanical support for the substrate. The combination stiffener and capacitor can also include first and second electrodes forming a capacitor. An electronic device package and a package substrate configured to receive the combination stiffener and capacitor are also disclosed.

公开(公告)号：US10796999B2

公开(公告)日：2020-10-06

申请号：US16284218

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Boon Ping Koh ,  Eng Huat Goh ,  Jiun Hann Sir ,  Khang Choong Yong ,  Min Suet Lim ,  Wil Choon Song

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor apparatus includes a floating-bridge interconnect that couples two semiconductive devices that are arranged across a middle semiconductive device. The floating-bridge interconnect can be semiconductive material such as a silicon bridge, or it can be an organic bridge. Computing functions required in one of the two semiconductive devices can be off-loaded to any of the floating-bridge interconnect or the other of the two semiconductive devices.

公开(公告)号：US10785872B2

公开(公告)日：2020-09-22

申请号：US16263370

申请日：2019-01-31

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Hoay Tien Teoh

IPC: H05K1/11 ,  H05K1/02 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18

Abstract: A jumper may be adapted to transmit an electrical signal. The jumper may be included in a system on a chip. The system on a chip may include a substrate, and the substrate may include one or more routing layers. The jumper may be included in the one or more routing layers of the substrate. A first interconnect may be positioned on a first side of the system on a chip, and a second interconnect may be positioned on a second side of the system on a chip. The jumper may be in electrical communication with the first interconnect, and may be in electrical communication with the second interconnect. The jumper may be electrically isolated from other components of the system on a chip, such as one or more die coupled to the substrate.

公开(公告)号：US20200137886A1

公开(公告)日：2020-04-30

申请号：US16565639

申请日：2019-09-10

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Eng Huat Goh ,  Jackson Chung Peng Kong ,  Khang Choong Yong ,  Min Suet Lim

IPC: H05K1/03 ,  H05K1/11 ,  H05K3/46 ,  H05K3/40

Abstract: To overcome the problem of the fiber weave effect desynchronizing differential signals in a pair of traces of approximately the same length in a printed circuit board, the pair of traces can be routed to traverse largely parallel paths that are above one another in the printed circuit board. The material between the paths can include weaved fiber bundles. The material on opposite sides of the paths, surrounding the pair of traces and the weaved fiber bundles, can include resin-rich material. As a result, the pair of traces are directly adjacent to the same materials, which can allow signals in the traces to propagate at the same speed, and prevent desynchronization of differential signals traversing the paths. The path length difference associated with traversing to different depths can be compensated with a relatively small in-plane diagonal jog of one of the traces.

公开(公告)号：US10606316B2

公开(公告)日：2020-03-31

申请号：US15778383

申请日：2015-12-10

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Kooi Chi Ooi ,  Bok Eng Cheah ,  Eng Huat Goh

IPC: G06F1/16 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/00 ,  H05K3/28

Abstract: A flexible electronic device that includes a flexible substrate having an upper surface and a lower surface and interconnects extending between the upper surface and the lower surface; a flexible display mounted directly to the upper surface of the flexible substrate such that the flexible display is electrically connected to the flexible substrate; a first encapsulant mounted to the upper surface of the flexible substrate such that the flexible display is at least partially embedded within the first encapsulant; an electronic component mounted to a lower surface of the flexible substrate such that the electronic component is electrically connected to the flexible substrate; a second encapsulant mounted to the lower surface of the flexible substrate such that the electronic component is at least partially embedded within the second encapsulant; a flexible casing that surrounds the electronic component and the second encapsulant.

公开(公告)号：US10438882B2

公开(公告)日：2019-10-08

申请号：US15473317

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： Eng Huat Goh

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/50 ,  H01L23/492 ,  H01L23/66 ,  H01L23/00

Abstract: Described herein are integrated circuit structures having a package substrate with microstrip transmission lines as the top metallization layer, and a ground plane external to the package substrate that is electrically connected to a ground plane internal to the package substrate, as well as related devices and methods. In one aspect of the present disclosure, an integrated circuit structure may include a package substrate having an internal ground plane and a microstrip signal layer as the top metallization layer, and an external ground plane on the surface of the package substrate that is electrically connected to the internal ground plane in the package substrate. In another aspect of the present disclosure, an integrated circuit structure may further include changes to microstrip transmission line geometry to match impedance values of areas covered by the external ground plane with impedance values of areas not covered by the external ground plane.

公开(公告)号：US10317938B2

公开(公告)日：2019-06-11

申请号：US14604531

申请日：2015-01-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Khai Ern See ,  Damien Weng Kong Chong ,  Min Suet Lim ,  Ping Ping Ooi ,  Chu Aun Lim ,  Jimmy Huat Since Huang ,  Poh Tat Oh ,  Teong Keat Beh ,  Jackson Chung Peng Kong ,  Fern Nee Tan ,  Jenn Chuan Cheng

IPC: G06F1/16 ,  H05K1/18 ,  G06F1/18 ,  G06F13/38

Abstract: Embodiments are generally directed to an apparatus utilizing computer on package construction. An embodiment of a computer includes a substrate; one or more semiconductor devices, the one or more semiconductor devices being direct chip attached to the substrate, the one or more semiconductor devices including a central processing unit (CPU); and one or more additional components installed on the substrate, wherein the computer excludes I/O components.

公开(公告)号：US10297541B2

公开(公告)日：2019-05-21

申请号：US15355961

申请日：2016-11-18

Applicant: Intel Corporation

Inventor： Min Suet Lim ,  Mooi Ling Chang ,  Eng Huat Goh ,  Say Thong Tony Tan ,  Tin Poay Chuah

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/538

Abstract: Microelectronic devices having a multiple-component substrate assembly. A primary supports one or more integrated circuits, and an auxiliary substrate is coupled to, and makes electrical connections with, the primary substrate. The primary substrate will define a pinout for some or all contacts of the integrated circuit, and the auxiliary substrate will provide an additional pinout option. Different configurations of a single primary substrate may be adapted to different applications through use of different configurations of auxiliary substrates.

公开(公告)号：US10256213B2

公开(公告)日：2019-04-09

申请号：US14964972

申请日：2015-12-10

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Min Suet Lim ,  Jiun Hann Sir

IPC: H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L25/00 ,  H01L27/108 ,  H01L23/31 ,  H01L25/10 ,  H01L25/18

Abstract: A computer memory module can include a molded layer disposed on a DRAM substrate. The molded layer can encapsulate a DRAM die and wire bonds that connect the DRAM die to the DRAM substrate, and can be shaped to include at least one cavity having a footprint sized to accommodate a system on chip (SOC) die. The DRAM module can attach to an SOC package so that the SOC die and the DRAM die are both positioned between the DRAM substrate and the SOC package, the DRAM substrate can form its electrical connections on only one side of the DRAM substrate, and the SOC die can fit at least partially into the cavity in the molded layer. This can reduce a package Z-height, compared to conventional DRAM packages in which the SOC die and the DRAM die are positioned on opposite sides of the DRAM substrate.

公开(公告)号：US10163777B2

公开(公告)日：2018-12-25

申请号：US15476905

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Seok Ling Lim ,  Eng Huat Goh ,  Hoay Tien Teoh ,  Jenny Shio Yin Ong ,  Jia Yan Go ,  Jiun Hann Sir ,  Min Suet Lim

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/043

Abstract: Interconnects for semiconductor packages are described. An apparatus may comprise a decoupling capacitor on a logic board, and a conductive interconnect element on the logic board, the conductive interconnect element to connect the decoupling capacitor on the logic board to a power conductor comprising a power pad of a semiconductor package, the conductive interconnect element at a different layer than a ground-potential layer of the logic board. Other embodiments are described and claimed.