公开(公告)号：US12191240B2

公开(公告)日：2025-01-07

申请号：US16539254

申请日：2019-08-13

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/64

Abstract: Embodiments disclosed herein include hybrid cores for electronic packaging applications. In an embodiment, a package substrate comprises a plurality of glass layers and a plurality of dielectric layers. In an embodiment, the glass layers alternate with the dielectric layers. In an embodiment, a through-hole through the plurality of glass layers and the plurality of dielectric layers is provided. In an embodiment a conductive through-hole via is disposed in the through-hole.

公开(公告)号：US20250006570A1

公开(公告)日：2025-01-02

申请号：US18883851

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Gang Duan ,  Srinivas Venkata Ramanuja Pietambaram ,  Jeremy Ecton ,  Brandon Christian Marin

IPC: H01L23/15 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: Glass cores including multiple layers and related methods are disclosed. An apparatus disclosed herein includes a printed circuit board and an integrated circuit package coupled to the printed circuit board, the integrated circuit package including a die and a glass core including a first layer having a first coefficient of thermal expansion and a second layer having a second coefficient of thermal expansion different than the first coefficient of thermal expansion.

公开(公告)号：US20240395661A1

公开(公告)日：2024-11-28

申请号：US18202046

申请日：2023-05-25

Applicant: Intel Corporation

Inventor： Numair Ahmed ,  Suddhasattwa Nad ,  Mohammad Mamunur Rahman ,  Brandon C. Marin ,  Sashi S. Kandanur ,  Srinivas Venkata Ramanuja Pietambaram ,  Darko Grujicic ,  Gang Duan ,  Banjamin Duong

IPC: H01L23/473 ,  H01L23/31 ,  H01L23/373 ,  H01L23/48 ,  H01L23/498

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a glass core layer having a first surface layer and a second surface layer; multiple channels within the glass core layer between the first surface and the second surface layer; and a first redistribution layer (RDL) including multiple sublayers of conductive traces formed in an organic material, wherein a first surface of the RDL contacts the first surface of the glass core layer.

公开(公告)号：US12125777B2

公开(公告)日：2024-10-22

申请号：US16666202

申请日：2019-10-28

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Gang Duan ,  Kemal Aygün ,  Jieying Kong ,  Brandon C. Marin

IPC: H01L23/49 ,  H01L21/48 ,  H01L23/498 ,  H01L23/66

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/66

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first buildup layer and a second buildup layer over the first buildup layer. In an embodiment, a void is disposed through the second buildup layer. In an embodiment the electronic package further comprises a first pad over the second buildup layer. In an embodiment, the first pad covers the void.

公开(公告)号：US20240222345A1

公开(公告)日：2024-07-04

申请号：US18090707

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Bai Nie ,  Srinivas Pietambaram ,  Gang Duan ,  Kyle Arrington ,  Ziyin Lin ,  Hongxia Feng ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu ,  Kristof Darmawikarta

IPC: H01L25/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/5383 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/05647 ,  H01L2224/08225 ,  H01L2224/80447 ,  H01L2224/80895

Abstract: An apparatus is provided which comprises: a plurality of interconnect layers within a substrate, a layer of organic dielectric material over the plurality of interconnect layers, copper pads within the layer of organic dielectric material, a first integrated circuit device copper-to-copper bonded with the copper pads, inorganic dielectric material over the layer of organic dielectric material, the inorganic dielectric material embedding the first integrated circuit device, and the inorganic dielectric material extending across a width of the substrate, and a second integrated circuit device coupled with a substrate surface above the inorganic dielectric material. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240222301A1

公开(公告)日：2024-07-04

申请号：US18147497

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Hongxia Feng ,  Haobo Chen ,  Srinivas Pietambaram ,  Bai Nie ,  Gang Duan ,  Kyle Arrington ,  Ziyin Lin ,  Yiqun Bai ,  Xiaoying Guo ,  Dingying Xu ,  Sairam Agraharam ,  Ashay Dani ,  Eric J. M. Moret ,  Tarek Ibrahim

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L2224/10122 ,  H01L2224/11011 ,  H01L2924/143 ,  H01L2924/186

Abstract: Methods and apparatus for optical thermal treatment in semiconductor packages are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, an interconnect associated with the dielectric substrate, and light absorption material proximate or surrounding the interconnect, the light absorption material to increase in temperature in response to being exposed to a pulsed light for thermal treatment corresponding to the IC package.

公开(公告)号：US20240222283A1

公开(公告)日：2024-07-04

申请号：US18147487

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Hongxia Feng ,  Bohan Shan ,  Bai Nie ,  Xiaoxuan Sun ,  Holly Sawyer ,  Tarek Ibrahim ,  Adwait Telang ,  Dingying Xu ,  Leonel Arana ,  Xiaoying Guo ,  Ashay Dani ,  Sairam Agraharam ,  Haobo Chen ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: Methods and apparatus to prevent over-etch in semiconductor packages are disclosed. A disclosed example semiconductor package includes at least one dielectric layer, an interconnect extending at least partially through or from the at least one dielectric layer, and a material on at least a portion of the interconnect, wherein the material comprises at least one of silicon or titanium.

公开(公告)号：US20240222282A1

公开(公告)日：2024-07-04

申请号：US18091150

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Sameer Paital ,  Gang Duan ,  Srinivas Pietambaram ,  Kristof Darmawikarta

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655

Abstract: Apparatuses, systems, assemblies, and techniques related to forming a metallization structure in a glass core package substrate such that the metallization structure has multiple portions with differing cross-sectional widths with little or no misalignment between the portions are described. Such techniques including mounting the glass core substrate to a stage, applying multiple laser exposures to a location of the glass core substrate to define laser treated regions of the glass core substrate corresponding to the portions of the metallization structure, removing the laser treated regions, and filling the openings with metal to form the embedded zero misaligned metallization structure.

公开(公告)号：US20240222259A1

公开(公告)日：2024-07-04

申请号：US18147535

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Xiyu Hu ,  Rhonda Jack ,  Catherine Mau ,  Hongxia Feng ,  Xiao Liu ,  Wei Wei ,  Srinivas Pietambaram ,  Gang Duan ,  Xiaoying Guo ,  Dingying Xu ,  Kyle Arrington ,  Ziyin Lin ,  Hiroki Tanaka ,  Leonel Arana

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/49894 ,  H01L21/481 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/16

Abstract: Methods, systems, apparatus, and articles of manufacture to produce integrated circuit (IC) packages having silicon nitride adhesion promoters are disclosed. An example IC package disclosed herein includes a metal layer on a substrate, a layer on the metal layer, the layer including silicon and nitrogen, and solder resist on the layer.

公开(公告)号：US20240222136A1

公开(公告)日：2024-07-04

申请号：US18091188

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Bohan Shan ,  Haobo Chen ,  Srinivas Venkata Ramanuja Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ashay A. Dani ,  Yiqun Bai ,  Dingying Xu ,  Bai Nie ,  Kyle Jordan Arrington ,  Wei Wei ,  Ziyin Lin

IPC: H01L21/321 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/3212 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76814 ,  H01L21/7684

Abstract: Mechanical or chemical processes can form roughened surfaces which can be used for coupling layers of electrical systems such as when forming dies, substrates, computer chips or the like that, when subjected to high stress, are robust enough to remain coupled together.