公开(公告)号：US20250006645A1

公开(公告)日：2025-01-02

申请号：US18343892

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Xiao Liu ,  Bohan Shan ,  Dingying Xu ,  Gang Duan ,  Haobo Chen ,  Hongxia Feng ,  Jung Kyu Han ,  Xiaoying Guo ,  Zhixin Xie ,  Xiyu Hu ,  Robert Alan May ,  Kristof Kuwawi Darmawikarta ,  Changhua Liu ,  Yosuke Kanaoka

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/15 ,  H01L23/31 ,  H01L23/58 ,  H01L25/10

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer of a substrate including a first material having a cavity and a conductive pad at a bottom of the cavity; a first microelectronic component having a first surface and an opposing second surface, the first microelectronic component in the cavity and electrically coupled to the conductive pad at the bottom of the cavity; a second layer of the substrate on the first layer of the substrate, the second layer including a second material that extends into the cavity and on and around the first microelectronic component, wherein the second material includes an organic photoimageable dielectric (PID) or an organic non-photoimageable dielectric (non-PID); and a second microelectronic component electrically coupled to the second surface of the first microelectronic component by conductive pathways through the second layer of the substrate.

公开(公告)号：US20250112165A1

公开(公告)日：2025-04-03

申请号：US18478250

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Brandon Marin ,  Hiroki Tanaka ,  Robert May ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Numair Ahmed ,  Jeremy Ecton ,  Benjamin Taylor Duong ,  Bai Nie ,  Haobo Chen ,  Xiao Liu ,  Bohan Shan ,  Shruti Sharma ,  Mollie Stewart

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: Anisotropic conductive connections for interconnect bridges and related methods are disclosed herein. An example a package substrate for an integrated circuit package, the package substrate comprising a first pad disposed at a first end of an interconnect within the package substrate, the first pad disposed in a cavity in the package substrate, an interconnect bridge disposed in the cavity, the interconnect bridge including a second pad, and a third pad, and a layer disposed between the first pad and the second pad, the layer having a first conductivity between the first pad and the second pad, the layer having a second conductivity between the second pad and the third pad, the first conductivity greater than the second conductivity.

公开(公告)号：US20240222259A1

公开(公告)日：2024-07-04

申请号：US18147535

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Haobo Chen ,  Bohan Shan ,  Xiyu Hu ,  Rhonda Jack ,  Catherine Mau ,  Hongxia Feng ,  Xiao Liu ,  Wei Wei ,  Srinivas Pietambaram ,  Gang Duan ,  Xiaoying Guo ,  Dingying Xu ,  Kyle Arrington ,  Ziyin Lin ,  Hiroki Tanaka ,  Leonel Arana

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/49894 ,  H01L21/481 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/16

Abstract: Methods, systems, apparatus, and articles of manufacture to produce integrated circuit (IC) packages having silicon nitride adhesion promoters are disclosed. An example IC package disclosed herein includes a metal layer on a substrate, a layer on the metal layer, the layer including silicon and nitrogen, and solder resist on the layer.