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    Programmable logic device with fine-grained disaggregation
    74.
    发明授权
    Programmable logic device with fine-grained disaggregation 有权

    公开(公告)号：US10601426B1

    公开(公告)日：2020-03-24

    申请号：US16123765

    申请日：2018-09-06

    Applicant: Intel Corporation

    Inventor： Dheeraj Subbareddy ,  Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Robert Sankman ,  Ravindranath Mahajan ,  Gregg William Baeckler

    IPC: H03K19/177 ,  H03K19/1776 ,  H01L25/18 ,  H01L23/367

    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.

    Rotatable Architecture for Multi-Chip Package (MCP)
    75.
    发明申请
    Rotatable Architecture for Multi-Chip Package (MCP) 审中-公开

    公开(公告)号：US20200006175A1

    公开(公告)日：2020-01-02

    申请号：US16022983

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy

    IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00

    Abstract: A multi-chip packaged device may include a first integrated circuit die with a first integrated circuit, such that the first integrated circuit may include a first plurality of ports disposed on a first side and a second plurality of ports disposed on a second side of the first integrated circuit die. The multi-chip packaged device may also include a second integrated circuit die, such that the second integrated circuit may include a third plurality of ports disposed on a third side of the second integrated circuit die. The first integrated circuit may communicate with the first side of the second integrated circuit when placed adjacent to the first side and communicate with the second side of the first integrated circuit die when placed adjacent to the second side.

    Techniques For Clock Signal Transmission In Integrated Circuits And Interposers
    76.
    发明申请
    Techniques For Clock Signal Transmission In Integrated Circuits And Interposers 审中-公开

    公开(公告)号：US20190227590A1

    公开(公告)日：2019-07-25

    申请号：US16367925

    申请日：2019-03-28

    Applicant: Intel Corporation

    Inventor： Jeffrey Chromczak ,  Chooi Pei Lim ,  Lai Guan Tang ,  Chee Hak Teh ,  MD Altaf Hossain ,  Dheeraj Subbareddy ,  Ankireddy Nalamalpu

    IPC: G06F1/10 ,  H01L23/31

    Abstract: A circuit system includes an interposer that has a first clock network and first and second integrated circuit dies that are mounted on the interposer. The first integrated circuit die includes a phase detector circuit, an adjustable delay circuit that generates a second clock signal in response to a first clock signal received from the first clock network, and a second clock network that generates a third clock signal in response to the second clock signal. The second integrated circuit die comprises a third clock network that generates a fourth clock signal in response to the first clock signal received from the first clock network. The phase detector circuit controls a delay provided by the adjustable delay circuit to the second clock signal based on a phase comparison between phases of the third and fourth clock signals.

    DUAL IN-LINE MEMORY MODULE (DIMM) PROGRAMMABLE ACCELERATOR CARD
    79.
    发明申请
    DUAL IN-LINE MEMORY MODULE (DIMM) PROGRAMMABLE ACCELERATOR CARD 审中-公开

    公开(公告)号：US20190108145A1

    公开(公告)日：2019-04-11

    申请号：US16211868

    申请日：2018-12-06

    Applicant: Intel Corporation

    Inventor： Sharath Raghava ,  Dheeraj Subbareddy ,  Kavitha Prasad ,  Ankireddy Nalamalpu ,  Harsha Gupta

    IPC: G06F13/16

    Abstract: A central processing unit (CPU) may be directly coupled to an accelerator dual in-line memory module (DIMM) card that is plugged into a DIMM slot. The CPU may include a master memory controller that sends requests or offloads tasks to the accelerator DIMM card via a low-latency double data rate (DDR) interface. The acceleration DIMM card may include a slave memory controller for translating the received requests, a decoder for decoding the translated requests, control circuitry for orchestrating the data flow within the DIMM card, hardware acceleration resources that can be dynamically programmed to support a wide variety of custom functions, and input-output components for interfacing with various types of non-volatile and/or volatile memory and for connecting with other types of storage and processing devices.

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