公开(公告)号：US20150350667A1

公开(公告)日：2015-12-03

申请号：US14737437

申请日：2015-06-11

Applicant: Intel Corporation

Inventor： Yi-Jen Chiu ,  Lidong Xu ,  Hong Jiang

IPC: H04N19/52 ,  H04N19/577

CPC classification number: H04N19/52 ,  H04N19/44 ,  H04N19/51 ,  H04N19/56 ,  H04N19/577

Abstract: Method and apparatus for deriving a motion vector at a video decoder. A block-based motion vector may be produced at the video decoder by utilizing motion estimation among available pixels relative to blocks in one or more reference frames. The available pixels could be, for example, spatially neighboring blocks in the sequential scan coding order of a current frame, blocks in a previously decoded frame, or blocks in a downsampled frame in a lower pyramid when layered coding has been used.

Abstract translation: 用于在视频解码器处导出运动矢量的方法和装置。 可以通过利用可用像素中相对于一个或多个参考帧中的块的运动估计在视频解码器处产生基于块的运动矢量。 当使用分层编码时，可用像素可以是例如当前帧的顺序扫描编码顺序的空间相邻块，先前解码的帧中的块，或者在使用分层编码时在较低金字塔中的下采样帧中的块。

公开(公告)号：US20150304682A1

公开(公告)日：2015-10-22

申请号：US14578802

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Lidong Xu ,  Yi-Jen Chiu ,  Wenhao Zhang

IPC: H04N19/577 ,  H04N19/44 ,  H04N19/172 ,  H04N19/103 ,  H04N19/139

CPC classification number: H04N19/577 ,  H04N19/103 ,  H04N19/137 ,  H04N19/139 ,  H04N19/172 ,  H04N19/44 ,  H04N19/513 ,  H04N19/52 ,  H04N19/57 ,  H04N19/573 ,  H04N19/61

Abstract: Methods and systems to apply motion estimation (ME) based on reconstructed reference pictures in a B frame or in a P frame at a video decoder. For a P frame, projective ME may be performed to obtain a motion vector (MV) for a current input block. In a B frame, both projective ME and mirror ME may be performed to obtain an MV for the current input block. The ME process can be performed on sub-partitions of the input block, which may reduce the prediction error without increasing the amount of MV information in the bitstream. Decoder-side ME can be applied for the prediction of existing inter frame coding modes, and traditional ME or the decoder-side ME can be adaptively selected to predict a coding mode based on a rate distribution optimization (RDO) criterion.

Abstract translation: 基于在B帧或视频解码器的P帧中的重建参考图像应用运动估计（ME）的方法和系统。 对于P帧，可以执行投影ME以获得当前输入块的运动矢量（MV）。 在B帧中，可以执行投射ME和镜ME两者以获得当前输入块的MV。 可以在输入块的子分区上执行ME处理，这可以在不增加比特流中的MV信息的量的情况下减少预测误差。 解码器端ME可以应用于现有的帧间编码模式的预测，并且传统的ME或解码器侧的ME可以被自适应地选择以基于速率分布优化（RDO）准则来预测编码模式。

公开(公告)号：US20150181216A1

公开(公告)日：2015-06-25

申请号：US14640356

申请日：2015-03-06

Applicant: Intel Corporation

Inventor： Wenhao Zhang ,  Yi-Jen Chiu ,  Lidong Xu ,  Yu Han ,  Zhipin Deng ,  Xiaoxia Cai

IPC: H04N19/159 ,  H04N19/182 ,  H04N19/513 ,  H04N19/105

CPC classification number: H04N19/159 ,  H04N19/105 ,  H04N19/117 ,  H04N19/136 ,  H04N19/147 ,  H04N19/176 ,  H04N19/182 ,  H04N19/30 ,  H04N19/33 ,  H04N19/34 ,  H04N19/503 ,  H04N19/513 ,  H04N19/59 ,  H04N19/80

Abstract: Systems, devices and methods are described including performing scalable video coding using inter-layer pixel sample prediction. Inter-layer pixel sample prediction in an enhancement layer coding unit, prediction unit, or transform unit may use reconstructed pixel samples obtained from a base layer or from a lower enhancement layer. The pixel samples may be subjected to upsample filtering and/or refinement filtering. The upsample or refinement filter coefficients may be predetermined or may be adaptively determined.

Abstract translation: 描述了使用层间像素样本预测执行可缩放视频编码的系统，设备和方法。 增强层编码单元，预测单元或变换单元中的层间像素样本预测可以使用从基本层或较低增强层获得的重建像素样本。 可以对像素样本进行上采样滤波和/或细化滤波。 上采样或细化滤波器系数可以是预定的或可以被自适应地确定。

公开(公告)号：US12190118B2

公开(公告)日：2025-01-07

申请号：US18339454

申请日：2023-06-22

Applicant: INTEL CORPORATION

Inventor： Christopher J. Hughes ,  Prasoonkumar Surti ,  Guei-Yuan Lueh ,  Adam T. Lake ,  Jill Boyce ,  Subramaniam Maiyuran ,  Lidong Xu ,  James M. Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Abhishek R. Appu

IPC: G06F9/38 ,  G06F9/50 ,  G06F9/54 ,  G06F12/084 ,  G06T1/60

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

公开(公告)号：US20240078630A1

公开(公告)日：2024-03-07

申请号：US18490593

申请日：2023-10-19

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Durgaprasad Bilagi ,  Joydeep Ray ,  Scott Janus ,  Sanjeev Jahagirdar ,  Brent Insko ,  Lidong Xu ,  Abhishek R. Appu ,  James Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Xinmin Tian ,  Guei-Yuan Lueh ,  Changliang Wang

IPC: G06T1/60 ,  G06F12/0802 ,  G06N5/04 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F12/0802 ,  G06N5/04 ,  G06T1/20 ,  G06F2212/251

Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

公开(公告)号：US11729416B2

公开(公告)日：2023-08-15

申请号：US16651641

申请日：2017-12-29

Applicant: INTEL CORPORATION

Inventor： Srinivasan Embar Raghukrishnan ,  James M. Holland ,  Sang-Hee Lee ,  Atthar H. Mohammed ,  Dmitry E. Ryzhov ,  Jason Tanner ,  Lidong Xu ,  Wenhao Zhang

IPC: H04N19/577 ,  H04N19/513 ,  H04N19/567 ,  H04N19/96

CPC classification number: H04N19/577 ,  H04N19/521 ,  H04N19/567 ,  H04N19/96

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a residual error based on coding unit information, and determine a candidate coding unit and an associated rate distortion cost based on the residual error. An embodiment may additionally or alternatively include technology to partition a first coding unit into two or more smaller coding units based on a partition message, accelerate processing of at least one of the two or more smaller coding units, and estimate motion fora frame based at least partially on results of the accelerated processing. Other embodiments are disclosed and claimed.

公开(公告)号：US11726793B2

公开(公告)日：2023-08-15

申请号：US17095585

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Prasoonkumar Surti ,  Guei-Yuan Lueh ,  Adam T. Lake ,  Jill Boyce ,  Subramaniam Maiyuran ,  Lidong Xu ,  James M. Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Abhishek R. Appu

IPC: G06F9/38 ,  G06F12/084 ,  G06T1/60 ,  G06F9/50 ,  G06F9/54

CPC classification number: G06F9/3891 ,  G06F9/5066 ,  G06F9/544 ,  G06F12/084 ,  G06T1/60

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

公开(公告)号：US11663746B2

公开(公告)日：2023-05-30

申请号：US17095544

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Prasoonkumar Surti ,  Jill Boyce ,  Subramaniam Maiyuran ,  Michael Apodaca ,  Adam T. Lake ,  James Holland ,  Vasanth Ranganathan ,  Altug Koker ,  Lidong Xu ,  Nikos Kaburlasos

IPC: G06T9/00 ,  G06T15/00 ,  G06N3/045

CPC classification number: G06T9/002 ,  G06N3/045 ,  G06T9/007 ,  G06T9/008 ,  G06T15/005

Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.

公开(公告)号：US20230054523A1

公开(公告)日：2023-02-23

申请号：US17793348

申请日：2020-02-17

Applicant: Intel Corporation

Inventor： Huan Dou ,  Lidong Xu ,  Xiaoxia Cai ,  Chen Wang ,  Yi-Jen Chiu

IPC: H04N5/232 ,  G06T5/00 ,  H04N19/597 ,  H04N19/80 ,  H04N19/86

Abstract: An example apparatus for enhancing video includes a decoder to decode a received 360-degree projection format video bitstream to generate a decoded 360-degree projection format video. The apparatus also includes a viewport generator to generate a viewport from the decoded 360-degree projection format video. The apparatus further includes a convolutional neural network (CNN)-based filter to remove an artifact from the viewport to generate an enhanced image. The apparatus further includes a displayer to send the enhanced image to a display.

公开(公告)号：US20220174304A1

公开(公告)日：2022-06-02

申请号：US17442056

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Lidong Xu

IPC: H04N19/46 ,  H04N19/136 ,  H04N19/172 ,  H04N19/167 ,  H04N19/146 ,  H04N19/42

Abstract: Embodiments of a video codec may include technology to derive a conformance point for a sub-region of coded pictures in a coded video sequence in the video data, group any combination of sub-pictures that form a rectangular region into a sub-picture set, and/or derive a level indicator corresponding to a sub-picture based on a level of the coded video sequence and a relative size of the coded picture and the sub-picture set. Other embodiments are disclosed and claimed.