公开(公告)号：US20230141181A1

公开(公告)日：2023-05-11

申请号：US18093069

申请日：2023-01-04

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore K. Muchherla

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0679 ,  G06F3/0646

Abstract: A method includes determining a respective number of and respective locations of valid data portions of a plurality of blocks of NAND memory cells, based on the respective locations of the valid data portions, determining respective dispersions of the valid data portions within the plurality of blocks of NAND memory cells, based at least on the respective dispersions, selecting a block of NAND memory cells from the plurality of blocks of NAND memory cells, and performing a folding operation on the selected block.

公开(公告)号：US11604601B2

公开(公告)日：2023-03-14

申请号：US17068327

申请日：2020-10-12

Applicant: Micron Technology, Inc.

Inventor： Steven Michael Kientz ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

Abstract: A memory sub-system to, in response to a power up, initiate a first loading process associated with a set of trim values, wherein the first loading process includes loading a sequence of the set of trim values to one or more registers of the memory sub-system. An operation associated with a memory unit of the memory sub-system is identified. A portion of the set of trim values corresponding to the operation associated with the memory unit is identified. The memory sub-system executes a second loading process comprising loading the portion of the set of trim values corresponding to the operation associated with the memory unit. The operation is executed using the portion of the set of trim values loaded into the one or more registers associated with the memory unit.

公开(公告)号：US20230076362A1

公开(公告)日：2023-03-09

申请号：US17984929

申请日：2022-11-10

Applicant: Micron Technology, Inc.

Inventor： Michael G. Miller ,  Ashutosh Malshe ,  Gianni Stephen Alsasua ,  Renato Padilla, JR. ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Harish Reddy Singidi

IPC: G06F3/06 ,  G06F11/07 ,  G11C16/26 ,  G11C16/34

Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.

公开(公告)号：US20230059923A1

公开(公告)日：2023-02-23

申请号：US17980234

申请日：2022-11-03

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Gianni S. Alsasua ,  Harish R. Singidi

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/10 ,  G06F12/0882 ,  G06F11/30 ,  G06F12/02 ,  G06F11/07

Abstract: A trigger rate associated with a scan operation of a set of memory pages of a data block is identified. The trigger rate is compared to a threshold rate to determine that a condition is satisfied. In response to satisfying the condition, a refresh operation is executed on the set of memory pages of the data block.

公开(公告)号：US20230057863A1

公开(公告)日：2023-02-23

申请号：US17981649

申请日：2022-11-07

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore K. Muchherla

IPC: G06F3/06

Abstract: A method includes determining that a ratio of valid data portions of a block of memory cells is greater than or less than a valid data portion threshold and performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions is greater than the valid data portion threshold. The method further includes performing a second media management operation on the block of memory cells in response to determining that the ratio of valid data portions is less than the valid data portion threshold.

公开(公告)号：US11527291B2

公开(公告)日：2022-12-13

申请号：US17062453

申请日：2020-10-02

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Harish R. Singidi ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe ,  Sampath K. Ratnam

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G11C16/30 ,  G11C16/08

Abstract: A request to perform a secure erase operation for a memory component can be received. A voltage level that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied to at least one wordline of the memory component to perform the secure erase operation. The voltage pulse can be associated with a program operation to place a memory cell of the memory component at another voltage level that exceeds the voltage level that is applied to the unselected wordlines of the memory component during the read operation.

公开(公告)号：US11521699B2

公开(公告)日：2022-12-06

申请号：US17085445

申请日：2020-10-30

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Gianni S. Alsasua ,  Harish R. Singidi

IPC: G06F11/30 ,  G11C29/42 ,  G11C29/44 ,  G11C29/10 ,  G06F12/0882 ,  G06F12/02 ,  G06F11/07

Abstract: A first scan operation of a set of memory pages of a data block is performed using a first reliability threshold level to identify a set of scan results. A workload type associated with the data block is determined based on the set of scan results. The first reliability threshold level is adjusted to a second reliability threshold level based on the workload type. A second scan operation of the set of memory pages of the data block is performed using the second reliability threshold level.

公开(公告)号：US11507317B2

公开(公告)日：2022-11-22

申请号：US17100334

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Sampath K. Ratnam ,  Yang Zhang ,  Guang Chang Ye ,  Kishore Kumar Muchherla ,  Hong Lu ,  Karl D. Schuh ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

Abstract: A program operation is executed on a memory sub-system. In response to receiving a request to execute a read operation, executing a first program suspend operation to suspend the program operation. In response to a completion of the read operation, a program resume operation is executed to resume execution of the program operation. A delay period is established following execution of the program resume operation during which execution of the program operation is completed. A second program suspend operation is executed following the delay period.

公开(公告)号：US11461158B2

公开(公告)日：2022-10-04

申请号：US15733561

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Qisong Lin ,  Vamsi Pavan Rayaprolu ,  Jiangang Wu ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Shao Chun Shi

IPC: G06F11/00 ,  G06F11/07

Abstract: A system includes a memory component to, upon completion of second pass programming in response to a multi-pass programming command, write flag bits within a group of memory cells programmed by the multi-pass programming command A processing device, operatively coupled to the memory component, is to perform multi-pass programming of the group of memory cells in association with a logical address. Upon receipt of a read request, the processing device is to determine that a second logical address within the read request does not match the logical address associated with data stored at a physical address of the group of memory cells. The processing device is further to determine a number of first values within the plurality of flag bits, and in response to the number of first values not satisfying a threshold criterion, report, to a host computing device, an uncorrectable data error.

公开(公告)号：US11456051B1

公开(公告)日：2022-09-27

申请号：US17212531

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Gary F. Besinga ,  Renato C. Padilla ,  Tawalin Opastrakoon ,  Sampath K. Ratnam ,  Michael G. Miller ,  Christopher M. Smitchger ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G11C29/44 ,  G11C29/42 ,  G11C16/26 ,  G11C29/00 ,  G11C16/10 ,  G11C29/50

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including receiving a set of read offsets for a block of the memory device, the set of read offsets comprising a default read offset, selecting the default read offset from the set of read offsets based on one or more criteria, applying the default read offset to a read operation performed with respect to the block, determining that a second set of criteria associated with removing the default read offset is satisfied, and removing the default read offset responsive to determining that the second set of criteria is satisfied.