公开(公告)号：US20250156316A1

公开(公告)日：2025-05-15

申请号：US19022410

申请日：2025-01-15

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Xiaolai Zhu ,  Deping He ,  Kulachet Tanpairoj ,  Hong Lu ,  Chun Sum Yeung

IPC: G06F12/02

Abstract: A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.

公开(公告)号：US11507317B2

公开(公告)日：2022-11-22

申请号：US17100334

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Sampath K. Ratnam ,  Yang Zhang ,  Guang Chang Ye ,  Kishore Kumar Muchherla ,  Hong Lu ,  Karl D. Schuh ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

Abstract: A program operation is executed on a memory sub-system. In response to receiving a request to execute a read operation, executing a first program suspend operation to suspend the program operation. In response to a completion of the read operation, a program resume operation is executed to resume execution of the program operation. A delay period is established following execution of the program resume operation during which execution of the program operation is completed. A second program suspend operation is executed following the delay period.

公开(公告)号：US20200285416A1

公开(公告)日：2020-09-10

申请号：US16294416

申请日：2019-03-06

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Sampath K. Ratnam ,  Yang Zhang ,  Guang Chang Ye ,  Kishore Kumar Muchherla ,  Hong Lu ,  Karl D. Schuh ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

Abstract: A program operation is executed on a memory sub-system. During execution of the program operation, a request to execute a read operation on the memory sub-system is received. In response to receiving the request, a program suspend operation to suspend the program operation is executed. The read operation is executed on the memory sub-system in response to a completion of the program suspend operation. In response to completion of the read operation, a program resume operation is executed. A program suspend delay period is established following execution of the program resume operation during which a subsequent read operation is stored in a queue.

公开(公告)号：US12210448B2

公开(公告)日：2025-01-28

申请号：US18037631

申请日：2022-09-01

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Xiaolai Zhu ,  Deping He ,  Kulachet Tanpairoj ,  Hong Lu ,  Chun Sum Yeung

IPC: G06F12/02

Abstract: A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.

公开(公告)号：US20250140323A1

公开(公告)日：2025-05-01

申请号：US18781524

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Kishore K. Muchherla ,  Hong Lu ,  Akira Goda ,  Shyam Sunder Raghunathan ,  Peter Feeley ,  Emilio Camerlenghi ,  Paolo Tessariol

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08

Abstract: An apparatus comprises a memory array comprising a plurality of physical blocks of memory cells each comprising more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block. A controller can operate the memory array in accordance with a logical block implementation in which each logical block comprises: a first erase block adjacent to a first end of a particular string corresponding to a first physical block; and a second erase block. The second erase block is either: located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block.

公开(公告)号：US20250077415A1

公开(公告)日：2025-03-06

申请号：US18771972

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Hong Lu ,  Mark Ish ,  Akira Goda

IPC: G06F12/02

Abstract: An apparatus can comprise a memory array comprising a plurality of erase blocks and a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller coupled to the memory array can be configured to: receive a write command corresponding to data to be written to the memory array; determine a temperature classification for the data to which the write command corresponds; and, based on the determined temperature classification for the data, route the data to a first write cursor or to one of a number of different write cursors.

公开(公告)号：US20240069776A1

公开(公告)日：2024-02-29

申请号：US18237737

申请日：2023-08-24

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Hong Lu ,  Kulachet Tanpairoj ,  Chun Sum Yeung ,  Jameer Mulani ,  Nitul Gohain ,  Uday Bhasker V. Vudugandla

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0673

Abstract: A system can include a memory device with multiple management units, each management unit made up of multiple blocks, and a processing device, operatively coupled with the memory device, to perform various operations including identifying, among the management units, some complete management units and some incomplete management units, as well as performing one type of operation using one or more complete management units. The operations can also include performing another type of operation using one or more incomplete management units where this other type of operation include writing, to one or more incomplete management units, metadata associated with the data stored in complete management units.

公开(公告)号：US20210072926A1

公开(公告)日：2021-03-11

申请号：US17100334

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Jiangang Wu ,  Sampath K. Ratnam ,  Yang Zhang ,  Guang Chang Ye ,  Kishore Kumar Muchherla ,  Hong Lu ,  Karl D. Schuh ,  Vamsi Pavan Rayaprolu

IPC: G06F3/06

Abstract: A program operation is executed on a memory sub-system. In response to receiving a request to execute a read operation, executing a first program suspend operation to suspend the program operation. In response to a completion of the read operation, a program resume operation is executed to resume execution of the program operation. A delay period is established following execution of the program resume operation during which execution of the program operation is completed. A second program suspend operation is executed following the delay period.

公开(公告)号：US20240345947A1

公开(公告)日：2024-10-17

申请号：US18037631

申请日：2022-09-01

Applicant: Micron Technology, Inc.

Inventor： Xiangang Luo ,  Jianmin Huang ,  Xiaolai Zhu ,  Deping He ,  Kulachet Tanpairoj ,  Hong Lu ,  Chun Sum Yeung

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A method includes writing, to a first data structure, indices corresponding to address locations of a logical-to-physical (L2P) data structure that maps a plurality of logical block addresses (LBAs) associated with the L2P data structure, initiating performance of a media management operation involving one or more memory blocks in which data associated with the LBAs is written, and refraining from rewriting particular entries in the L2P table that correspond to LBAs whose index in the first data structure is a particular value during performance of the media management operation.

公开(公告)号：US20240311057A1

公开(公告)日：2024-09-19

申请号：US18606670

申请日：2024-03-15

Applicant: Micron Technology, Inc.

Inventor： Daniel J. Hubbard ,  Kishore K. Muchherla ,  Hong Lu ,  Xiangang Luo ,  Akira Goda

IPC: G06F3/06

CPC classification number: G06F3/0679 ,  G06F3/0614 ,  G06F3/0659

Abstract: A method can comprise receiving data corresponding to a sequence of write commands to write the data to a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings comprises: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block having a first programming characteristic; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block having a second programming characteristic. The method can further comprise writing data sequentially to the first erase blocks of the plurality of strings and the second erase blocks of the plurality of strings in an interleaved manner by: writing a first portion of the data to one or more first erase blocks of the plurality of strings; and writing, subsequent to writing the first portion of the data to the one or more first erase blocks, a second portion of the data to one or more second erase blocks of the plurality of strings.