公开(公告)号：US10860417B1

公开(公告)日：2020-12-08

申请号：US16530469

申请日：2019-08-02

Applicant: Micron Technology, Inc.

Inventor： Wolfgang Anton Spirkl ,  Thomas Hein ,  Peter Mayer ,  Michael Dieter Richter ,  Martin Brox

IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06

Abstract: Methods, systems, and devices for multiple memory die techniques are described. A memory device may include multiple memory dies and may be configured to communicate with a host device. For example, each memory die may be coupled with a set of data pins that includes respective subsets of data pins (e.g., a set of eight data pins having two subsets of four data pins). Further, each memory die may have one or more auxiliary pins used for channel coding information for data communicated over one or more of the subsets of data pins. In some cases, each memory die may include one or more additional auxiliary pins, which may be used for channel coding information for a respective subset of data pins or multiple subsets of data pins. The channel coding information associated with the auxiliary pin(s) may include error detection code information, data coding information, or any combination thereof.

公开(公告)号：US20200233741A1

公开(公告)日：2020-07-23

申请号：US16744025

申请日：2020-01-15

Applicant: Micron Technology, Inc.

Inventor： Martin Brox ,  Peter Mayer ,  Wolfgang Anton Spirki ,  Thomas Hein ,  Michael Dieter Richter ,  Timothy M. Hollis ,  Roy E. Greeff

IPC: G06F11/10 ,  G06F12/02 ,  G06F11/16

Abstract: Methods, systems, and devices for channel modulation for a memory device are described. A system may include a memory device and a host device coupled with the memory device. The system may be configured to communicate a first signal modulated using a first modulation scheme and communicate a second signal that is based on the first signal and that is modulated using a second modulation scheme. The first modulation scheme may include a first quantity of voltage levels that span a first range of voltages, and the second modulation scheme may include a second quantity of voltage levels that span a second range of voltages different than (e.g., smaller than) the first range of voltages. The first signal may include write data carried over a data channel, and the second signal may include error detection information based on the write data that is carried over an error detection channel.

公开(公告)号：US20200159441A1

公开(公告)日：2020-05-21

申请号：US16674955

申请日：2019-11-05

Applicant: Micron Technology, Inc.

Inventor： Peter Mayer ,  Thomas Hein ,  Wolfgang Anton Spirkl ,  Martin Brox ,  Michael Dieter Richter

IPC: G06F3/06

Abstract: Methods, systems, and devices for temperature-based memory management are described. A system may include a memory device and a host device. The host device may identify a temperature (e.g., of the memory device). The host device may determine a value for a parameter for operating the memory device—such as a timing, voltage, or frequency parameter—based on the temperature of the memory device. The host device may transmit signaling to the memory device or another component of the system based on the value of the parameter. In some cases, the host device may determine the temperature of the memory device based on an indication (e.g., provided by the memory device). In some cases, the host device may determine the temperature of the memory device based on a temperature of the host device or a temperature of another component of the system.

公开(公告)号：US20200065185A1

公开(公告)日：2020-02-27

申请号：US16538537

申请日：2019-08-12

Applicant: Micron Technology, Inc.

Inventor： Peter Mayer ,  Thomas Hein ,  Martin Brox ,  Wolfgang Anton Spirkl ,  Michael Dieter Richter

IPC: G06F11/10 ,  G11C29/42

Abstract: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

公开(公告)号：US12300597B2

公开(公告)日：2025-05-13

申请号：US18652515

申请日：2024-05-01

Applicant: Micron Technology, Inc.

Inventor： David K. Ovard ,  Thomas Hein ,  Timothy M. Hollis ,  Walter L. Moden

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498

Abstract: Systems may include a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA), or any combination thereof. At least one memory device may be connected to the CPU, the GPU, or the FPGA. The memory device(s) may include a device substrate including a microelectronic device and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on the package substrate. Each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal may be located only diagonally adjacent to any other balls of the ball grid array configured to carry another of a high-bandwidth data signal or a high-frequency clock signal.

公开(公告)号：US20250029673A1

公开(公告)日：2025-01-23

申请号：US18765074

申请日：2024-07-05

Applicant: Micron Technology, Inc.

Inventor： Ronny Schneider ,  Marcos Alvarez Gonzalez ,  Casto Salobrena Garcia ,  Michael Dieter Richter ,  Thomas Hein ,  Mohammad Aasim Ekhtiyar

IPC: G11C29/44

Abstract: Methods, systems, and devices for bit inversion techniques for memory system repair indications are described. A memory system may store an address of a failed access line or an inversion of the address based on a quantity of bits having a first bit value. For example, if an address has a quantity of ‘1’s that is greater than a threshold, the memory system may store an inversion of the address by inverting the address and setting one-time programmable (OTP) elements to indicate the inverted ‘1’s. The memory system may also store an additional inversion bit to indicate the inversion of the address. For reading the OTP elements, the memory system may interpret an address as inverted or non-inverted based on the inversion bit. The memory system may also indicate one or more steps of a repair process to a host system to facilitate communication during repair procedures.

公开(公告)号：US20250028598A1

公开(公告)日：2025-01-23

申请号：US18763967

申请日：2024-07-03

Applicant: Micron Technology, Inc.

Inventor： Michael Dieter Richter ,  Thomas Hein ,  Casto Salobrena Garcia

IPC: G06F11/10 ,  G06F11/14

Abstract: Methods, systems, and devices for maintaining integrity of configuration data for memory devices are described. A memory system may implement an error control component configured to detect errors in configuration data stored to one or more mode registers. The error control component may be configured to generate error control information, including one or more parity bits or a checksum, associated with the configuration data. The memory system or a host system coupled with the memory system may be configured to detect errors in the configuration data based on the error control information. Based on detecting the errors, the memory system may enter a safe mode, in which the memory system refrains from performing access operations until the configuration data is rewritten to the one or more mode registers.

公开(公告)号：US20250013534A1

公开(公告)日：2025-01-09

申请号：US18762327

申请日：2024-07-02

Applicant: Micron Technology, Inc.

Inventor： Michael Dieter Richter ,  Casto Salobrena Garcia ,  Wolfgang Anton Spirkl ,  Thomas Hein ,  Peter Mayer

IPC: G06F11/10

Abstract: Methods, systems, and devices for techniques for data path address protection are described. As part of a write operation, the memory system may receive data associated with the write operation and an address for the data from a host system. The memory system may generate a first codeword using the address and may store both the first codeword and the data at the address. In some examples, the memory system may generate a second codeword using the data and the first codeword and store the second codeword along with the data and the first codeword. As part of a subsequent read operation for the data, the memory system may receive the address from the host system and retrieve the stored data and first codeword. The memory system may generate a third codeword using the address associated with the read operation and may compare the third codeword with the first codeword.

公开(公告)号：US20250013525A1

公开(公告)日：2025-01-09

申请号：US18737831

申请日：2024-06-07

Applicant: Micron Technology, Inc.

Inventor： Wolfgang Anton Spirkl ,  Casto Salobrena Garcia ,  Michael Dieter Richter ,  Thomas Hein ,  Peter Mayer

IPC: G06F11/07 ,  G06F11/30

Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. A first set of parameters associated with operating an interface between a host system and a memory system may be determined based on a first training operation, where an indication of the first set of parameters and a first temperature associated with the first training operation may be stored. A second set of parameters associated with operating the interface may be determined based on a second training operation, where an indication of the second set of parameters and a second temperature associated with the second training operation may be stored. At a third temperature, a third set of parameters may be configured for operation of the interface based on the stored sets of parameters, and communications over the interface may be performed in accordance with the third set of parameters.

公开(公告)号：US20240402935A1

公开(公告)日：2024-12-05

申请号：US18732845

申请日：2024-06-04

Applicant: Micron Technology, Inc.

Inventor： Peter Mayer ,  Thomas Hein ,  Wolfgang Anton Spirkl ,  Martin Brox ,  Michael Dieter Richter

IPC: G06F3/06 ,  G11C7/04 ,  G11C11/4074

Abstract: Methods, systems, and devices for temperature-based memory management are described. A system may include a memory device and a host device. The host device may identify a temperature (e.g., of the memory device). The host device may determine a value for a parameter for operating the memory device—such as a timing, voltage, or frequency parameter—based on the temperature of the memory device. The host device may transmit signaling to the memory device or another component of the system based on the value of the parameter. In some cases, the host device may determine the temperature of the memory device based on an indication (e.g., provided by the memory device). In some cases, the host device may determine the temperature of the memory device based on a temperature of the host device or a temperature of another component of the system.