公开(公告)号：US20240061588A1

公开(公告)日：2024-02-22

申请号：US17889873

申请日：2022-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yu-Chung Lien ,  Zhenming Zhou

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0644

Abstract: A program command specifying new data to be programmed is received and partitioned into a plurality of data partitions. A wordline addressing a first set of memory cells to be programmed with a data partition of the plurality of data partitions is identified for a specified block of the memory device. Existing data stored by a second set of memory cells is read. An expected data state metrics is produced for each data partition of the plurality of data partitions. A data partition associated with a lowest expected data state metric among the plurality of expected data state metrics is identified. The identified data partition is programmed to the identified wordline.

公开(公告)号：US20240053901A1

公开(公告)日：2024-02-15

申请号：US17888080

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Ching-Huang Lu ,  Zhenming Zhou

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0679 ,  G06F3/0653 ,  G06F3/0659

Abstract: Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A bitline voltage is determined using the cycle number and the group. The command is executed using the bitline voltage.

公开(公告)号：US20240053896A1

公开(公告)日：2024-02-15

申请号：US17888171

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Zhenming Zhou ,  Murong Lang ,  Ching-Huang Lu

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0679

Abstract: Methods, systems, and apparatuses include receiving a command directed to a portion of memory. A cycle number for the portion of memory is determined. A group to which the portion of memory belongs is determined. A sensing time is determined using the cycle number and the group. The command is executed using the sensing time.

公开(公告)号：US20240046998A1

公开(公告)日：2024-02-08

申请号：US17879356

申请日：2022-08-02

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Ching-Huang Lu ,  Zhenming Zhou

IPC: G11C16/30

CPC classification number: G11C16/30

Abstract: Apparatus and methods are disclosed, including an apparatus that includes a set of memory components of a memory sub-system. The set of memory components include a first memory block comprising first units of linearly arranged memory cells and a second memory block comprising second units of linearly arranged memory cells. The set of memory components include a slit portion dividing the first and second memory blocks. The slit portion includes a capacitor in which a first metal portion of the capacitor is adjacent to the first units of linearly arranged memory cells and a second metal portion of the capacitor is adjacent to the second units of linearly arranged memory cells.

公开(公告)号：US20240046981A1

公开(公告)日：2024-02-08

申请号：US17881180

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Zhenming Zhou

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  G11C11/4074 ,  G11C11/4076

Abstract: A memory subsystem receives a first read command and a second read command. Responsive to determining that the first read command originated from a host system, the memory subsystem selects a reverse read trim setting. Responsive to determining that the second read command did not originate from the host system, the memory subsystem selects a forward read trim setting. The memory subsystem executes the first read command using the reverse read trim setting. The memory subsystem executes the second read command using the forward read trim setting.

公开(公告)号：US20240029802A1

公开(公告)日：2024-01-25

申请号：US17871689

申请日：2022-07-22

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Murong Lang ,  Li-Te Chang

IPC: G11C16/34 ,  G11C11/406

CPC classification number: G11C16/3418 ,  G11C16/349 ,  G11C11/40618

Abstract: An example system can include a memory device and a processing device. The memory device can include a group of memory cells. The processing device can be coupled to the memory device. The processing device can be configured to determine a distance of a memory die from a center of a memory component. The processing device can be configured to perform a read disturb operation on the memory die based on the determined distance use a first voltage window for a set of memory cells of the group of memory cells during a first time period.

公开(公告)号：US20230395162A1

公开(公告)日：2023-12-07

申请号：US17938153

申请日：2022-10-05

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Tingjun Xie ,  Fangfang Zhu ,  Jiangli Zhu ,  Zhenming Zhou

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/12

CPC classification number: G11C16/26 ,  G11C16/102 ,  G11C16/12

Abstract: Methods, apparatuses and systems related to protecting an apparatus against unauthorized accesses or usages are described. The apparatus may include a data protection circuit that protects an operating state of the apparatus, data stored in the apparatus, or a combination thereof when a temperature of the apparatus is outside of an operating range thereof.

公开(公告)号：US20230395152A1

公开(公告)日：2023-12-07

申请号：US17876346

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Murong Lang ,  Fangfang Zhu ,  Jiangli Zhu ,  Zhenming Zhou

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/08

CPC classification number: G11C16/102 ,  G11C16/26 ,  G11C16/32 ,  G11C16/08

Abstract: A method includes performing, over a time period, a quantity of write operations associated with a quad-level cell (QLC) memory block, determining the time period exceeds a threshold time, designating the QLC memory block as a bimodal, determining a voltage threshold level of a last successful read operation associated with the QLC memory block, and setting a read threshold level of at least a portion of the QLC memory block at the voltage threshold level of the last successful read operation.

公开(公告)号：US20230393776A1

公开(公告)日：2023-12-07

申请号：US17830625

申请日：2022-06-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhenming Zhou ,  Murong Lang ,  Ching-Huang Lu ,  Nagendra Prasad Ganesh Rao

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0679 ,  G06F3/0604 ,  G06F3/0652

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request to perform a read operation on a segment of the memory device; determining a program erase cycle count associated with the segment of the memory device; determining a temperature offset value for the segment of the memory device based on a write temperature and a read temperature, determining whether the temperature offset value satisfies a threshold criterion associated with the program erase cycle count of the segment; and responsive to determining that the temperature offset value satisfies the threshold criterion, performing a corrective read operation on the segment of the memory device, wherein a sense time parameter of the corrective read operation is modified according to the temperature offset value and the program erase cycle count.

公开(公告)号：US11790998B2

公开(公告)日：2023-10-17

申请号：US17411278

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhenming Zhou ,  Zhenlei Shen ,  Charles See Yeung Kwong

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3418 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26

Abstract: A plurality of memory units residing in a first location of a memory device is identified, wherein the first location of the memory device corresponds to a first layer of a plurality of layers of the memory device. It is determined whether a write disturb capability associated with the first location of the memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of logical addresses associated with the plurality of memory units is remapped to a second location of the memory device, wherein the second location of the memory device corresponds to a second layer of the plurality of layers of the memory device, and wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.