公开(公告)号：US20070205956A1

公开(公告)日：2007-09-06

申请号：US11712361

申请日：2007-02-28

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01Q7/00

CPC classification number: H01F5/003 ,  H01F5/00 ,  H01F17/0006 ,  H01F27/29 ,  H01L23/3114 ,  H01L23/525 ,  H01L23/645 ,  H01L24/11 ,  H01L24/12 ,  H01L25/16 ,  H01L2223/6677 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/351 ,  H01Q1/2283 ,  H01Q1/243 ,  H01Q7/00 ,  H01Q21/28 ,  H01L2924/00 ,  H01L2224/05599

Abstract: An electronic substrate including: a base substrate having an active face and a rear face; and a plurality of inductor elements formed on or above the active face, or formed on or above the rear face.

Abstract translation: 一种电子基板，包括：具有活性面和背面的基底基板; 以及形成在有源面上或上方的多个电感器元件，或形成在后表面上或上方。

公开(公告)号：US20070205855A1

公开(公告)日：2007-09-06

申请号：US11708170

申请日：2007-02-19

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01F5/00

CPC classification number: H01F5/003 ,  H01F17/0006 ,  H01F17/0013 ,  H01F27/292 ,  H01F38/14 ,  H01L2224/16 ,  H01Q1/2266 ,  H01Q1/2283 ,  H01Q1/38

Abstract: An electronic substrate includes: a base substrate having an active face and a rear face; inductor elements formed on or above the active face, and formed on or above the rear face; and a conductive member electrically connected to the inductor element formed on or above the rear face, penetrating through the base substrate from the active face to the rear face.

Abstract translation: 电子基板包括：具有活性面和背面的基底基板; 电感元件形成在有源面上或上方，形成在后表面上或上面; 以及导电构件，其电连接到形成在所述后表面上或上方的所述电感器元件，所述导电构件穿过所述基底基板从所述主动面到所述后表面。

公开(公告)号：US07184276B2

公开(公告)日：2007-02-27

申请号：US10895386

申请日：2004-07-21

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H01L23/49838 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15331 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671

Abstract: A semiconductor device includes a plurality of semiconductor chips; and a plurality of substrates, each of the substrates having one of the semiconductor chips mounted thereon. The substrates are stacked each other. The upper and lower ones of the semiconductor chips mounted on a pair of the stacked substrates are electrically connected through first terminals provided in a region outside the region in which one of the semiconductor chips is mounted in each of the substrates. The lowest one of the substrates has second terminals provided in its region closer to its center than its region in which the first terminals are provided, the second terminals electrically connected to one of the semiconductor chips. A pitch of adjacent two of the second terminals is wider than a pitch of adjacent two of the first terminals.

Abstract translation: 半导体器件包括多个半导体芯片; 和多个基板，每个基板上安装有一个半导体芯片。 基板彼此堆叠。 安装在一对堆叠的基板上的半导体芯片的上下半导体通过设置在其中一个半导体芯片安装在每个基板中的区域之外的区域中的第一端子电连接。 最底层的一个基板具有在其区域中比设置有第一端子的区域更靠近其中心的区域设置第二端子，第二端子电连接到一个半导体芯片。 相邻的两个第二端子的间距比相邻的两个第一端子的间距宽。

公开(公告)号：US07169643B1

公开(公告)日：2007-01-30

申请号：US09615503

申请日：2000-07-13

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L21/00

CPC classification number: H01L21/67132 ,  H01L21/4871 ,  H01L23/4985 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/50 ,  H01L2224/73265 ,  H01L2924/07811 ,  H01L2924/15311 ,  Y10T29/41 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device comprising: a step (a) of attaching a plurality of semiconductor chips to a tape; a step (b) of cutting the tape; and a step (c) of providing a plurality of external terminals on an insulating film cut from the tape, wherein the steps (a) and (b) are carried out in a reel-to-reel transport system.

Abstract translation: 一种制造半导体器件的方法，包括：将多个半导体芯片附着到带上的步骤（a）; 切割带的步骤（b）; 以及在从所述带切割的绝缘膜上设置多个外部端子的步骤（c），其中步骤（a）和（b）在卷对卷输送系统中进行。

公开(公告)号：US07163613B2

公开(公告)日：2007-01-16

申请号：US10923874

申请日：2004-08-24

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: C25D5/16 ,  C25D5/02 ,  C25D5/00 ,  C25D7/06

CPC classification number: H01L24/86 ,  H01L21/563 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/07811 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/0393 ,  H05K1/112 ,  H05K3/242 ,  H05K3/243 ,  H05K3/323 ,  H05K3/422 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/0394 ,  H05K2203/049 ,  H05K2203/072 ,  H05K2203/0733 ,  H05K2203/1476 ,  H05K2203/1545 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671

Abstract: There is provided a semiconductor device comprising: a first plating layer formed on one surface of an interconnect pattern; a second plating layer formed within through holes in the interconnect pattern; a semiconductor chip electrically connected to the first plating layer; an anisotropic conductive material provided on the first plating layer; and a conductive material provided on the second plating layer, wherein the first plating layer has appropriate adhesion properties with the anisotropic conductive material, and the second plating layer has appropriate adhesion properties with the conductive material.

Abstract translation: 提供了一种半导体器件，包括：形成在互连图案的一个表面上的第一镀层; 形成在所述互连图案中的通孔内的第二镀层; 电连接到第一镀层的半导体芯片; 设置在第一镀层上的各向异性导电材料; 以及设置在所述第二镀层上的导电材料，其中所述第一镀层与所述各向异性导电材料具有适当的粘合性，并且所述第二镀层与所述导电材料具有适当的粘合性能。

公开(公告)号：US20060278983A1

公开(公告)日：2006-12-14

申请号：US11433901

申请日：2006-05-12

Applicant: Haruki Ito ,  Nobuaki Hashimoto

Inventor： Haruki Ito ,  Nobuaki Hashimoto

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L23/4824 ,  H01L23/50 ,  H01L23/522 ,  H01L24/12 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H03H9/0547 ,  H03H9/0552 ,  H03H9/1071 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/01074 ,  H01L2924/01023

Abstract: A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.

公开(公告)号：US07129420B2

公开(公告)日：2006-10-31

申请号：US11295630

申请日：2005-12-07

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H05K1/16

CPC classification number: H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15331 ,  Y10T29/49126 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671

Abstract: A semiconductor device includes a semiconductor chip and a substrate having an interconnecting pattern formed thereover. The substrate has the semiconductor chip mounted on one surface thereof. The substrate has an outline larger than the semiconductor chip. First terminals are formed in a region outside the region of the substrate in which the semiconductor chip is mounted. Second terminals are a part of the interconnecting pattern which exposes its surface opposite to its surface opposing the semiconductor chip in a region closer to a center of the substrate than the first terminals. The semiconductor chip is electrically connected to the first and second terminals.

Abstract translation: 半导体器件包括半导体芯片和在其上形成有互连图案的基板。 基板具有安装在其一个表面上的半导体芯片。 衬底的轮廓大于半导体芯片。 第一端子形成在安装有半导体芯片的基板的区域外的区域中。 第二端子是互连图案的一部分，其在比第一端子更靠近基板的中心的区域中暴露出与其与半导体芯片相对的表面相对的表面。 半导体芯片电连接到第一和第二端子。

公开(公告)号：US07119445B2

公开(公告)日：2006-10-10

申请号：US11274150

申请日：2005-11-16

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L23/48 ,  H01L27/146 ,  H01L27/148

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/49575 ,  H01L23/525 ,  H01L23/562 ,  H01L25/0652 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83101 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/00012

Abstract: An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device (10) having a semiconductor chip (12) with electrodes (16), a stress-relieving layer (14) prepared on the semiconductor chip (12), a wire (18) formed across the electrodes (16) and the stress-relieving layer (14), and solder balls (19) formed on the wire (18) over the stress-relieving layer (14); and a bare chip (20) as a second semiconductor device to be electrically connected to the first semiconductor device (10).

公开(公告)号：US07094629B2

公开(公告)日：2006-08-22

申请号：US10954294

申请日：2004-10-01

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L21/44

CPC classification number: H01L24/10 ,  H01L21/486 ,  H01L21/563 ,  H01L23/13 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/3457 ,  H05K3/386 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0394 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05647 ,  H01L2224/05099 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: The semiconductor device comprises an insulating film in which penetrating holes are formed, a semiconductor chip having electrodes, a wiring pattern adhered by an adhesive over a region including penetrating holes on one side of the insulating film and electrically connected to the electrodes of the semiconductor chip, and external electrodes provided on the wiring pattern through the penetrating holes and projecting from the surface opposite to the surface of the substrate on which the wiring pattern is formed. Part of the adhesive is drawn in to be interposed between the penetrating holes and external electrodes.

公开(公告)号：US07067741B2

公开(公告)日：2006-06-27

申请号：US10361566

申请日：2003-02-11

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H05K1/16

CPC classification number: H01L23/49805 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15331 ,  Y10T29/49126 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671

Abstract: A semiconductor device includes a semiconductor chip and a substrate having an interconnecting pattern formed thereover. The substrate has the semiconductor chip mounted on one surface thereof. The substrate has an outline larger than the semiconductor chip. First terminals are formed in a region outside the region of the substrate in which the semiconductor chip is mounted. Second terminals are a part of the interconnecting pattern which exposes its surface opposite to its surface opposing the semiconductor chip in a region closer to a center of the substrate than the first terminals. The semiconductor chip is electrically connected to the first and second terminals.