公开(公告)号：US20240029804A1

公开(公告)日：2024-01-25

申请号：US17868956

申请日：2022-07-20

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Xiaochen Zhu ,  Jiahui Yuan ,  Lito De La Rama

IPC: G11C16/34 ,  G11C16/16

CPC classification number: G11C16/3445 ,  G11C16/16 ,  G11C16/349 ,  G11C11/407

Abstract: An apparatus is provided that includes a block of memory cells and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a first count of a number of times that the block of memory cells previously has been programmed and erased, determining a threshold number based on the first count, and determining whether the erase operation passed or failed based on the threshold number.

公开(公告)号：US20240006002A1

公开(公告)日：2024-01-04

申请号：US17852786

申请日：2022-06-29

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Jiacen Guo ,  Jiahui Yuan

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/16 ,  G11C16/32 ,  G11C16/30

CPC classification number: G11C16/3459 ,  G11C16/3404 ,  G11C16/102 ,  G11C16/16 ,  G11C16/32 ,  G11C16/30

Abstract: To remedy short term data retention issues, a system creates a gate to channel voltage differential for non-volatile memory cells between programming and verifying in order to accelerate the effects of the short term data retention issue. That is, the gate to channel voltage differential will accelerate the migrating of electrons out of shallow traps. In some embodiments, the gate to channel voltage differential comprises a higher voltage at the channel in comparison to the gate. In some embodiments, the programming comprises applying doses of a programming signal and the gate to channel voltage differential is only created for a subset of the time periods between doses of the programming signal.

公开(公告)号：US20230368846A1

公开(公告)日：2023-11-16

申请号：US17740429

申请日：2022-05-10

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiaochen Zhu ,  Xiang Yang ,  Lito De La Rama ,  Yi Song ,  Jiahui Yuan

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/28 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

Abstract: Technology is disclosed herein for a memory system that compensates for different programming speeds in two sets of memory cells when reading those two sets of memory cells. The memory system programs a group of the memory cells to one or more data states. In one aspect, the memory cells are not verified during programming. The group has a first set of memory cells that program at a first speed and a second set of memory cells that program at a second speed. The memory system reads the first set of the memory cells with a first set of read parameters and reads the second set of the memory cells with a second set of read parameters. The first set of read parameters are different from the second set of read parameters to compensate for the different programming speeds.

公开(公告)号：US20230328973A1

公开(公告)日：2023-10-12

申请号：US17716698

申请日：2022-04-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely Said ,  Raghuveer S. Makala ,  Jiahui Yuan ,  Senaka Kanakamedala

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528

CPC classification number: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/5283

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and a drain-select-level isolation structure. One of the insulating layers is a composite insulating layer including an insulating-material-containing sublayer consisting essentially of an insulating material and an etch stop dielectric material sublayer having a material composition that is different from the insulating material. The etch stop dielectric material sublayer can be employed as an etch stop structure during formation of the drain-select-level isolation structure through drain-select-level electrically conductive layers.

公开(公告)号：US20230326530A1

公开(公告)日：2023-10-12

申请号：US17715647

申请日：2022-04-07

Applicant: SanDisk Technologies LLC

Inventor： Chin-Yi Chen ,  Muhammad Masuduzzaman ,  Kou Tei ,  Deepanshu Dutta ,  Hiroyuki Mizukoshi ,  Jiahui Yuan ,  Xiang Yang

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C11/5621

Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.

公开(公告)号：US20230317169A1

公开(公告)日：2023-10-05

申请号：US17709762

申请日：2022-03-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Xiaochen Zhu ,  Lito De La Rama ,  Yi Song ,  Jiacen Guo ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  H01L25/0657 ,  G11C16/0483

Abstract: A non-volatile memory system limits the amount of programming for a first type of group of non-volatile memory cells based on a first parameter such that a maximum number of programming pulses applied to the first type of group of non-volatile memory cells to program to the last data state after the first type of group of non-volatile memory cells completed programming to the other data states is X programming pulses. The non-volatile memory system limits the amount of programming for a second type of group of the non-volatile memory cells based on a second parameter such that a maximum number of programming pulses applied to the second type of group of non-volatile memory cells to program to the last data state after the second type of group of non-volatile memory cells completed programming to the other data states is Y programming pulses.

公开(公告)号：US20230290403A1

公开(公告)日：2023-09-14

申请号：US17690332

申请日：2022-03-09

Applicant: SanDisk Technologies LLC

Inventor： Jiahui Yuan ,  Kai Kirk ,  Yu-Chung Lien

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  G11C11/4074 ,  G11C11/4076

Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine whether the apparatus is in low power mode; in response to determining that the apparatus is in low power mode, perform a normal order read operation on a set of memory cells of the plurality of memory cells; and in response to determining that the apparatus is not in low power mode, perform a reverse order read operation on the set of memory cells of the plurality of memory cells.

公开(公告)号：US20230058038A1

公开(公告)日：2023-02-23

申请号：US17404217

申请日：2021-08-17

Applicant: SanDisk Technologies LLC

Inventor： Abu Naser Zainuddin ,  Jia Li ,  Jiahui Yuan ,  Bo Lei

IPC: G11C16/16 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04

Abstract: Apparatuses and techniques are described for modifying program and erase parameters in a memory device in which memory cells can be operated in a single bit per cell (SLC) mode or a multiple bits per cell mode. In one approach, the stress on a set of memory cells in an SLC mode is reduced during programming and erasing when the number of program-erase cycles for the block in the SLC mode is below a threshold. For example, during programming, the program-verify voltage and program voltages can be reduced to provide a shallower than normal programming. During erasing, the erase-verify voltage can be increased while the erase voltages can be reduced to provide a shallower than normal erase. When the number of program-erase cycles for the block in the SLC mode is above the threshold, the program and erase parameters revert to a default levels.

公开(公告)号：US20220415398A1

公开(公告)日：2022-12-29

申请号：US17360677

申请日：2021-06-28

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Jiahui Yuan ,  Deepanshu Dutta

IPC: G11C16/08 ,  G11C16/04

Abstract: A memory device is provided in which blocks of memory cells are divided into separate portions or sub-blocks with respective sets of word line switching transistors. The sub-blocks can be arranged on a substrate on opposite sides of a dividing line, where a separate set of bit lines is provided on each side of the dividing line. Each block has a row decoder which provides a common word line voltage signal to each sub-block of the block. However, each sub-block can have an independent set of word line switching transistors so that the common word line voltage signal can be passed or blocked independently for each sub-block. The blocks of memory cells can be provided on a first die which is inverted and bonded to a second die which includes the sets of word line switching transistors.

公开(公告)号：US11475957B2

公开(公告)日：2022-10-18

申请号：US17149560

申请日：2021-01-14

Applicant: SanDisk Technologies LLC

Inventor： Abu Naser Zainuddin ,  Dongxiang Liao ,  Jiahui Yuan

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11565 ,  H01L27/11582

Abstract: Apparatuses and techniques are described for optimizing programming in a memory device in which memory cells can be programmed using single bit per cell programming and multiple bits per cell programming. In one aspect, a single bit per cell program operation is performed which reduces damage to the memory cells as well as reducing program time. The program operation can omit a pre-charge phase and a verify phase of an initial program loop of a program operation. Instead, a program phase is performed followed by a recovery phase. In one or more subsequent program loops of the single bit per cell program operation, as well as in each program loop of a multiple bit per cell program operation, the program loop includes a pre-charge phase, a program phase, a recovery phase and a verify phase.