公开(公告)号：US09257280B2

公开(公告)日：2016-02-09

申请号：US14294278

申请日：2014-06-03

Applicant: TOKYO ELECTRON LIMITED

Inventor： Akiteru Ko ,  Angelique D. Raley ,  Kiyohito Ito

IPC: H01L21/308 ,  H01L21/33 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/31144

Abstract: A method which is particularly advantageous for improving a Self-Aligned Pattern (SAP) etching process. In such a process, facets formed on a spacer layer can cause undesirable lateral etching in an underlying layer beneath the spacer layer when the underlying layer is to be etched. This detracts from the desired vertical form of the etch. The etching of the underlying layer is performed in at least two steps, with a passivation layer or protective layer formed between the etch steps, so that sidewalls of the underlying layer that was partially etched during the initial etching are protected. After the protective layer is formed, the etching of the remaining portions of the underlying layer can resume.

Abstract translation: 一种特别有利于改进自对准图案（SAP）蚀刻工艺的方法。 在这种过程中，当衬底层被蚀刻时，形成在间隔层上的刻面可能在间隔层下面的下层中产生不期望的横向蚀刻。 这会损害所需垂直形式的蚀刻。 底层的蚀刻在至少两个步骤中进行，其中在蚀刻步骤之间形成钝化层或保护层，使得在初始蚀刻期间被部分蚀刻的下层的侧壁被保护。 在形成保护层之后，可以恢复下层的其余部分的蚀刻。

公开(公告)号：US09159575B2

公开(公告)日：2015-10-13

申请号：US14282716

申请日：2014-05-20

Applicant: Tokyo Electron Limited

Inventor： Alok Ranjan ,  Akiteru Ko

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01J37/32 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L21/3065 ,  H01J37/32082 ,  H01J37/3211 ,  H01J37/32137 ,  H01J37/32146 ,  H01J37/32165 ,  H01J37/3222 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32697 ,  H01J37/32706 ,  H01J2237/334 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/67069 ,  H01L21/6831 ,  H01L29/517 ,  H01L29/518

Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).

Abstract translation: 描述了在基板上构图栅叠层的方法。 该方法包括在衬底上准备栅极堆叠，其中栅极堆叠包括形成在高k层上的高k层和栅极层。 该方法还包括使用脉冲偏压等离子体蚀刻工艺将形成在栅极层中的图案转移到高k层，以及选择用于脉冲偏压等离子体蚀刻工艺的工艺条件，以实现在衬底中形成的具有深度 小于2纳米（nm）。

公开(公告)号：US20240027900A1

公开(公告)日：2024-01-25

申请号：US17871444

申请日：2022-07-22

Applicant: Tokyo Electron Limited

Inventor： Hamed Hajibabaeinajafabadi ,  Akiteru Ko

IPC: G03F7/004 ,  G03F7/42 ,  G03F7/40 ,  G03F7/32

CPC classification number: G03F7/0043 ,  G03F7/426 ,  G03F7/40 ,  G03F7/325

Abstract: A method of reactive developing a metal oxide resist includes providing a gaseous weak acid to a surface of a patterned metal oxide resist including an exposed portion and an unexposed portion, the gaseous weak acid having an acidity (pKa) greater than −2 and less than about 20, and reactive developing the patterned metal oxide resist using a selective acid-base reaction between the gaseous weak acid and the patterned metal oxide resist to form volatile products. The gaseous weak acid acts as the acid and either the exposed portion or the unexposed portion acts as the base.

公开(公告)号：US11557479B2

公开(公告)日：2023-01-17

申请号：US16824346

申请日：2020-03-19

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Akiteru Ko ,  Subhadeep Kal ,  Toshiharu Wada

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027

Abstract: Methods process microelectronic workpieces with inverse extreme ultraviolet (EUV) patterning processes. In part, the inverse patterning techniques are applied to reduce or eliminate defects experienced with conventional EUV patterning processes. The inverse patterning techniques include additional process steps as compared to the conventional EUV patterning processes, such as an overcoat process, an etch back or planarization process, and a pattern removal process. In addition, further example embodiments combine inverse patterning techniques with line smoothing treatments to reduce pattern roughness and achieve a target level of line roughness. By using this additional technique, line pattern roughness can be significantly improved in addition to reducing or eliminating microbridge and/or other defects.

公开(公告)号：US20220392771A1

公开(公告)日：2022-12-08

申请号：US17735800

申请日：2022-05-03

Applicant: Tokyo Electron Limited

Inventor： Akiteru Ko

IPC: H01L21/308 ,  H01L21/3065 ,  H01L21/027

Abstract: A method of processing a substrate that includes receiving a patterned photoresist formed over a substrate, the patterned photoresist defining initial openings, each of the initial openings including a first side and an opposite second side along a first direction; depositing a mask material preferentially on the first side within the initial openings using an oblique deposition process performed at a first angle inclined from the first side; and removing a portion of the patterned photoresist using an oblique etch process performed at a second angle inclined from the second side, the mask material and a remaining portion of the patterned photoresist defining final openings.

公开(公告)号：US10978300B2

公开(公告)日：2021-04-13

申请号：US16507821

申请日：2019-07-10

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213

Abstract: Embodiments are disclosed that reduce gouging during multi-patterning processes using thermal decomposition materials. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as cores during multiple patterning processes. For one embodiment, gouging is reduced or suppressed by using thermal decomposition materials as a gap fill material during multiple patterning processes. By using thermal decomposition material, gouging of an underlying layer, such as a hard mask layer, can be reduced or suppressed for patterned structures being formed using the self-aligned multi-patterning processes because more destructive etch processes, such as plasma etch processes, are not required to remove the thermal decomposition materials.

公开(公告)号：US20210050214A1

公开(公告)日：2021-02-18

申请号：US16988170

申请日：2020-08-07

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Akiteru Ko

IPC: H01L21/033

Abstract: Embodiments are described herein that apply capping layers to cores prior to spacer formation in self-aligned multiple patterning (SAMP) processes to achieve vertical spacer profiles. For one embodiment, a plasma process is used to deposit a capping layer on cores, and this capping layer causes resulting core profiles to have protective caps. These protective caps formed with the additional capping layer help to reduce or minimize material loss and corner loss of the core material during spacer deposition and spacer etch processes. This reduction in core material loss improves the resulting spacer profile so that a more vertical profile is achieved. For one embodiment, an angle of 80-90 degrees is achieved for vertical sidewalls of the spacers adjacent core sites with respect to the horizontal surface of the underlying layer, such as a hard mask layer formed on a substrate for a microelectronic workpiece.

公开(公告)号：US10916428B2

公开(公告)日：2021-02-09

申请号：US16290580

申请日：2019-03-01

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/033

Abstract: A process is provided in which a patterned layer, an intervening layer and a first layer to be etched according to the pattern of the patterned layer are formed. The intervening layer may be a thermal decomposition layer that may be removed by a heat based removal process. After etching the first layer, the use of a heat based removal process may allow the intervening layer to be removed from the substrate without altering the first layer. In one embodiment, the first layer may be a memorization layer and the process may be a multiple patterning process.

公开(公告)号：US20200328082A1

公开(公告)日：2020-10-15

申请号：US16836239

申请日：2020-03-31

Applicant: Tokyo Electron Limited

Inventor： Akiteru Ko

IPC: H01L21/033 ,  C23C14/34 ,  G03F7/20 ,  G03F7/30 ,  G03F7/16 ,  H01L29/66

Abstract: A method includes providing a substrate including mandrels of a first material positioned on an underlying layer. Each of the mandrels includes a first sidewall and an opposing second sidewall. The method further includes forming sidewall spacers made of a second material and including a first sidewall spacer abutting each respective first sidewall and a second sidewall spacer abutting each respective second sidewall. The mandrels extend above top surfaces of the sidewall spacers. The method also includes forming first capped sidewall spacers by depositing a third material on the first sidewall spacers without depositing on the second sidewall spacers, forming second capped sidewall spacers by depositing a fourth material on the second sidewall spacers without depositing on the first sidewall spacers, and selectively removing at least one of the first material, the second material, the third material, and the fourth material to uncover an exposed portion of the underlying layer.

公开(公告)号：US20200020534A1

公开(公告)日：2020-01-16

申请号：US16290580

申请日：2019-03-01

Applicant: Tokyo Electron Limited

Inventor： Yuki Kikuchi ,  Toshiharu Wada ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/033

Abstract: A process is provided in which a patterned layer, an intervening layer and a first layer to be etched according to the pattern of the patterned layer are formed. The intervening layer may be a thermal decomposition layer that may be removed by a heat based removal process. After etching the first layer, the use of a heat based removal process may allow the intervening layer to be removed from the substrate without altering the first layer. In one embodiment, the first layer may be a memorization layer and the process may be a multiple patterning process.