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    Semiconductor device
    74.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11521895B2

    公开(公告)日：2022-12-06

    申请号：US17325125

    申请日：2021-05-19

    Applicant: United Microelectronics Corp.

    Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Chich-Neng Chang

    IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

    Abstract: A structure of semiconductor device includes a substrate, having a dielectric layer on top. The structure further includes at least two metal elements being adjacent, disposed in the dielectric layer, wherein an air gap is existing between the two metal elements. The air gap has a cross-section of substantially bottle shape with a flat top. A porous dielectric layer is disposed over the substrate, sealing the flat top of the air gap. An inter-layer dielectric layer disposed on the porous dielectric layer.

    MRAM STRUCTURE AND METHOD OF FABRICATING THE SAME
    75.
    发明申请
    MRAM STRUCTURE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220246839A1

    公开(公告)日：2022-08-04

    申请号：US17725511

    申请日：2022-04-20

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Da-Jun Lin ,  Min-Hua Tsai ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

    IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

    Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile material pieces.

    METHOD FOR FABRICATING MEMORY CELL OF MAGNETORESISTIVE RANDOM ACCESS MEMORY
    76.
    发明申请
    METHOD FOR FABRICATING MEMORY CELL OF MAGNETORESISTIVE RANDOM ACCESS MEMORY 有权

    公开(公告)号：US20220140229A1

    公开(公告)日：2022-05-05

    申请号：US17573641

    申请日：2022-01-12

    Applicant: United Microelectronics Corp.

    Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ting-An Chien

    IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10

    Abstract: A method for fabricating memory cell of magnetoresistive RAM includes forming a memory stack structure on a first electrode layer. The memory stack structure includes a SAF layer to serve as a pinned layer; a magnetic free layer and a barrier layer sandwiched between the SAF layer and the magnetic free layer. A second electrode layer is then formed on the memory stack structure. The SAF layer includes a first magnetic layer, a second magnetic layer, and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first and second magnetic layers, and the second metal element of the first magnetic layer and the second magnetic layer interfaces with the spacer layer.

    Magnetoresistive random access memory device and method for fabricating the same
    78.
    发明授权
    Magnetoresistive random access memory device and method for fabricating the same 有权

    公开(公告)号：US11258005B2

    公开(公告)日：2022-02-22

    申请号：US16656304

    申请日：2019-10-17

    Applicant: United Microelectronics Corp.

    Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ting-An Chien

    IPC: H01L43/12 ,  H01L43/02 ,  H01L43/10

    Abstract: A cell structure of magnetoresistive RAM includes a synthetic anti-ferromagnetic (SAF) layer to serve as a pinned layer; a barrier layer, disposed on the SAF layer; and a magnetic free layer, disposed on the barrier layer. The SAF layer includes: a first magnetic layer; a second magnetic layer; and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first magnetic layer and the second magnetic layer interfacing with the spacer layer.

    Memory cell and forming method thereof
    80.
    发明授权
    Memory cell and forming method thereof 有权

    公开(公告)号：US11101324B2

    公开(公告)日：2021-08-24

    申请号：US16513719

    申请日：2019-07-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ya-Jyuan Hung ,  Chin-Chia Yang ,  Ting-An Chien

    IPC: H01L27/24 ,  H01L27/28 ,  H01L45/00 ,  H01L51/00 ,  H01L51/05 ,  H01L51/10

    Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

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