公开(公告)号：US20240365563A1

公开(公告)日：2024-10-31

申请号：US18762663

申请日：2024-07-03

Applicant: UNITED MICROELECTRONICS CORP

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen ,  Wei Chen

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device including a magnetic tunneling junction (MTJ) and a hard mask on a substrate, a first inter-metal dielectric (IMD) layer around the MTJ, a first metal interconnection adjacent to the MTJ, a first barrier layer and a channel layer on the first IMD layer to directly contact the hard mask and electrically connect the MTJ and the first metal interconnection, and a stop layer around the channel layer.

公开(公告)号：US12108680B2

公开(公告)日：2024-10-01

申请号：US18135758

申请日：2023-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Yu-Ping Wang

IPC: H10N50/01 ,  H10N50/80 ,  H10B61/00 ,  H10N50/85

CPC classification number: H10N50/01 ,  H10N50/80 ,  H10B61/00 ,  H10N50/85

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.

公开(公告)号：US20240315095A1

公开(公告)日：2024-09-19

申请号：US18135741

申请日：2023-04-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chuan-Lan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Chu-Fu Lin ,  Chun-Ting Yeh ,  Chung-Hsing Kuo ,  Yi-Feng Hsu

IPC: H10K59/131

CPC classification number: H10K59/131

Abstract: A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.

公开(公告)号：US12052933B2

公开(公告)日：2024-07-30

申请号：US18132992

申请日：2023-04-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Rai-Min Huang ,  I-Fan Chang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01

Abstract: The present invention provides a semiconductor device, the semiconductor device includes a metal interconnection on a substrate, in which a top view of the metal interconnection comprises a quadrilateral; and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a top view of the MTJ comprises a circular shape, an area of the MTJ is smaller than an area of the metal interconnection.

公开(公告)号：US20240215260A1

公开(公告)日：2024-06-27

申请号：US18595376

申请日：2024-03-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/80

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spin orbit torque (SOT) layer on the MTJ, a passivation layer around the MTJ, and a second SOT layer on the first SOT layer and the passivation layer. Preferably, a top surface of the passivation layer is lower than a top surface of the first SOT layer.

公开(公告)号：US20240162401A1

公开(公告)日：2024-05-16

申请号：US18078103

申请日：2022-12-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chuan-Lan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Chun-Ting Yeh

IPC: H01L33/62 ,  H01L25/075

CPC classification number: H01L33/62 ,  H01L25/0753 ,  H01L2933/0066

Abstract: A method for fabricating a micro display device includes the steps of providing a wafer comprising a first area, a second area, and a third area, forming first bonding pads on the first area, forming second bonding pads on the second area, and forming third bonding pads on the third area. Preferably, the first bonding pads and the second bonding pads are made of different materials and the first bonding pads and the third bonding pads are made of different materials.

公开(公告)号：US11968910B2

公开(公告)日：2024-04-23

申请号：US17500971

申请日：2021-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin

IPC: H10N52/01 ,  H10B61/00 ,  H10N52/00 ,  H10N52/80

CPC classification number: H10N52/01 ,  H10B61/00 ,  H10N52/00 ,  H10N52/80

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming an etch stop layer on the MTJ stack, forming a first spin orbit torque (SOT) layer on the etch stop layer, and then patterning the first SOT layer, the etch stop layer, and the MTJ stack to form a MTJ.

公开(公告)号：US20240107895A1

公开(公告)日：2024-03-28

申请号：US18528707

申请日：2023-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Jian-Cheng Chen ,  Yu-Ping Wang ,  Yu-Ruei Chen

IPC: H10N50/80 ,  G11C11/16 ,  H01L27/02 ,  H10B61/00

CPC classification number: H10N50/80 ,  G11C11/161 ,  H01L27/0207 ,  H10B61/22

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

公开(公告)号：US11849648B2

公开(公告)日：2023-12-19

申请号：US17341417

申请日：2021-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Yi-Wei Tseng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H10N50/80 ,  H01L29/82 ,  G11C11/16 ,  G11C5/06 ,  H10N50/01 ,  H10N50/10 ,  H10B61/00

CPC classification number: H10N50/80 ,  G11C5/06 ,  G11C11/16 ,  G11C11/161 ,  H01L29/82 ,  H10N50/01 ,  H10N50/10 ,  G11C2211/5615 ,  H10B61/00

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

公开(公告)号：US11849592B2

公开(公告)日：2023-12-19

申请号：US17888451

申请日：2022-08-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  I-Fan Chang ,  Rai-Min Huang ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H10B61/00 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L23/522 ,  H01L23/528 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/34 ,  H01L23/528 ,  H01L23/5226 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a substrate having a logic region and a magnetoresistive random access memory (MRAM) region, a MTJ on the MRAM region, a metal interconnection on the MTJ, and a blocking layer on the metal interconnection. Preferably, the blocking layer includes a stripe pattern according to a top view and the blocking layer could include metal or a dielectric layer.