公开(公告)号：US20140256115A1

公开(公告)日：2014-09-11

申请号：US14285645

申请日：2014-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Liu ,  Chia-Lung Chang ,  Jei-Ming Chen ,  Jui-Min Lee ,  Yuh-Min Lin

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L29/0649

Abstract: A semiconductor structure is located in a recess of a substrate. The semiconductor structure includes a liner, a silicon rich layer and a filling material. The liner is located on the surface of the recess. The silicon rich layer is located on the liner. The filling material is located on the silicon rich layer and fills the recess. Furthermore, a semiconductor process forming said semiconductor structure is also provided.

Abstract translation: 半导体结构位于衬底的凹部中。 半导体结构包括衬垫，富硅层和填充材料。 衬垫位于凹槽的表面上。 富硅层位于衬套上。 填充材料位于富硅层上并填充凹槽。 此外，还提供了形成所述半导体结构的半导体工艺。

公开(公告)号：US20140213034A1

公开(公告)日：2014-07-31

申请号：US13752408

申请日：2013-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lung Chang ,  Chih-Chien Liu ,  Jei-Ming Chen ,  Wen-Yi Teng ,  Jui-Min Lee ,  Keng-Jen Lin ,  Chin-Fu Lin

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76232

Abstract: A method for forming an isolation structure includes the following steps. A hard mask layer is formed on a substrate and a trench is formed in the substrate and the hard mask layer. A protective layer is formed to cover the trench and the hard mask layer. A first isolation material is filled into the trench. An etching process is performed to etch back part of the first isolation material.

Abstract translation: 形成隔离结构的方法包括以下步骤。 在基板上形成硬掩模层，并且在基板和硬掩模层中形成沟槽。 形成保护层以覆盖沟槽和硬掩模层。 第一隔离材料被填充到沟槽中。 执行蚀刻工艺以蚀刻第一隔离材料的一部分。

公开(公告)号：US20140134824A1

公开(公告)日：2014-05-15

申请号：US13677318

申请日：2012-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jei-Ming Chen ,  Wen-Yi Teng ,  Chia-Lung Chang ,  Chih-Chien Liu

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/3105 ,  H01L21/76229 ,  H01L21/76819 ,  H01L21/76826 ,  H01L21/76837

Abstract: A method of fabricating a dielectric layer includes the following steps. At first, a dielectric layer is formed on a substrate, and a chemical mechanical polishing (CMP) process is performed on the dielectric layer. Subsequently, a surface treatment process is performed on the dielectric layer after the chemical mechanical polishing process, and the surface treatment process includes introducing an oxygen plasma.

Abstract translation: 制造介电层的方法包括以下步骤。 首先，在基板上形成电介质层，对电介质层进行化学机械研磨（CMP）处理。 随后，在化学机械抛光工艺之后对电介质层进行表面处理工艺，并且表面处理工艺包括引入氧等离子体。

公开(公告)号：US08709901B1

公开(公告)日：2014-04-29

申请号：US13864277

申请日：2013-04-17

Applicant: United Microelectronics Corp.

Inventor： Chia-Lung Chang ,  Wu-Sian Sie ,  Jei-Ming Chen ,  Wen-Yi Teng ,  Chih-Chien Liu ,  Jui-Min Lee ,  Chih-Hsun Lin

IPC: H01L21/336

CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/32105

Abstract: The present invention relates to a method of forming an isolation structure, in which, a trench is formed in a substrate through a hard mask, and deposition, etch back, deposition, planarization, and etch back are performed in the order to form an isolation material layer of the isolation structure after the hard mask is removed. A silicon layer may be formed to cover the trench and original surface of the substrate before the former deposition, or to cover a part of the trench and original surface of the substrate after the former etch back and before the later deposition, to serve as a stop layer for the planarization process. Voids existing within the isolation material layer can be exposed or removed by partially etching the isolation material layer by the former etch back. The later deposition can be performed with a less aspect ratio to avoid forming voids.

Abstract translation: 本发明涉及一种形成隔离结构的方法，其中通过硬掩模在衬底中形成沟槽，并且进行沉积，回蚀刻，沉积，平坦化和回蚀以形成隔离 去除硬掩模后隔离结构的材料层。 可以形成硅层以在前一次沉积之前覆盖衬底的沟槽和原始表面，或者在前面的回蚀刻和稍后的沉积之前覆盖衬底的一部分沟槽和原始表面，以用作 停止层进行平面化处理。 存在于隔离材料层内的空隙可以通过由前面的回蚀部分蚀刻隔离材料层而被暴露或去除。 可以以较小的纵横比进行后续沉积以避免形成空隙。

公开(公告)号：US20140091395A1

公开(公告)日：2014-04-03

申请号：US13633094

申请日：2012-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chien Liu ,  Tzu-Chin Wu ,  Yu-Shu Lin ,  Jei-Ming Chen ,  Wen-Yi Teng

IPC: H01L21/336 ,  H01L27/088 ,  H01L21/28

CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653

Abstract: A method for fabricating a transistor device including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.). Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a lower tensile stress than the second tensile stress layer.

Abstract translation: 一种晶体管器件的制造方法，包括以下工序。 首先，提供具有第一晶体管区域的半导体衬底。 进行低温沉积工艺以在第一晶体管区域内的晶体管上形成第一拉伸应力层，其中低温沉积工艺的温度低于300摄氏度（℃）。 然后，进行高温退火处理，其中高温退火工艺的温度比低温沉积工艺的温度高至少150℃。 最后，在第一拉伸应力层上形成第二拉伸应力层，其中第一拉伸应力层具有比第二拉伸应力层低的拉伸应力。

公开(公告)号：US08476164B1

公开(公告)日：2013-07-02

申请号：US13661111

申请日：2012-10-26

Applicant: United Microelectronics Corp.

Inventor： Chin-Fu Lin ,  Chin-Cheng Chien ,  Chih-Chien Liu ,  Chia-Lin Hsu ,  Chun-Yuan Wu

IPC: H01L21/44

CPC classification number: H01L29/665 ,  H01L29/78 ,  H01L29/7845

Abstract: A method of manufacturing semiconductor device is provided. A substrate at least with a patterned silicon-containing layer on the substrate and spacers adjacent to the patterned silicon-containing layer is provided. A metal layer is formed on the substrate and covers the patterned silicon-containing layer and spacers. Then, a capping layer is formed on the metal layer. A first rapid thermal process is performed to at least make a portion of the metal layer react with the substrate around the spacers to form transitional silicides. The capping layer and the unreacted portions of the metal layer are removed. A first nitride film with a first tensile stress S1 is formed on the substrate. A second rapid thermal process is performed to transfer the transitional silicide to a silicide and transfer the first nitride film to a second nitride film with a second tensile stress S2, wherein S2>S1.

Abstract translation: 提供一种制造半导体器件的方法。 提供至少在衬底上具有图案化的含硅层的衬底和与图案化的含硅层相邻的衬垫。 在基板上形成金属层，并覆盖图案化的含硅层和间隔物。 然后，在金属层上形成覆盖层。 进行第一快速热处理以至少使金属层的一部分与衬垫周围的衬底反应以形成过渡的硅化物。 除去覆盖层和金属层的未反应部分。 在基板上形成具有第一拉伸应力S1的第一氮化物膜。 执行第二快速热处理以将过渡硅化物转移到硅化物，并将第一氮化物膜转移到具有第二拉伸应力S2的第二氮化物膜，其中S2> S1。