公开(公告)号：US20170263732A1

公开(公告)日：2017-09-14

申请号：US15481419

申请日：2017-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Yi-Fan Li ,  Kun-Hsin Chen ,  Tong-Jyun Huang ,  Jyh-Shyang Jenq ,  Nan-Yuan Huang

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26546 ,  H01L29/1054 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A semiconductor device preferably includes a substrate, a fin-shaped structure on the substrate, a buffer layer on the fin-shaped structure, and an epitaxial layer on the buffer layer. Preferably, the buffer layer is made of silicon germanium and including three or more than three elements. The buffer layer also includes dopants selected from the group consisting of P, As, Sb, Bi, C, and F.

公开(公告)号：US09735047B1

公开(公告)日：2017-08-15

申请号：US15172161

申请日：2016-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L21/336 ,  H01L21/768 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L23/532 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/7682 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/28132 ,  H01L21/28141 ,  H01L21/2815 ,  H01L21/28247 ,  H01L21/31105 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823864 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66689 ,  H01L29/66719

Abstract: A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and the spacer is composed of a single material. The gate structure includes a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, in which the high-k dielectric layer is U-shaped. The semiconductor device also includes an interlayer dielectric (ILD) layer around the gate structure and a hard mask on the spacer, in which the top surface of the hard mask is even with the top surface of the ILD layer.

公开(公告)号：US09711394B1

公开(公告)日：2017-07-18

申请号：US15161301

申请日：2016-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L21/00 ,  H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L29/41791

Abstract: A method for fabricating a semiconductor device includes the following steps: providing a substrate having an epitaxial layer, a gate structure and an interlayer dielectric thereon, where the epitaxial structure is disposed at sides of the gate structure and the interlayer dielectric covering the epitaxial structure; forming an opening in the interlayer dielectric so that the surface of the epitaxial layer is exposed from the bottom of the opening; performing a rapid thermal process in an inert environment until non-conductive material is generated on the surface of the epitaxial layer; and removing the non-conductive material.

公开(公告)号：US20170194203A1

公开(公告)日：2017-07-06

申请号：US15014034

申请日：2016-02-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/06 ,  H01L21/033 ,  H01L29/66 ,  H01L23/535 ,  H01L21/8234 ,  H01L27/11 ,  H01L29/08

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/1104 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7851

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a first and second fin shaped structures, a first and second gate structures and a first and second plugs. The first and second fin shaped structures are disposed on a first region and a second region of a substrate and the first and second gate structure are disposed across the first and second fin shaped structures, respectively. A dielectric layer is disposed on the substrate, covering the first and second gate structure. The first and second plugs are disposed in the dielectric layer, wherein the first plug is electrically connected first source/drain regions adjacent to the first gate structure and contacts sidewalls of the first gate structure, and the second plug is electrically connected to second source/drain regions adjacent to the second gate structure and not contacting sidewalls of the second gate structure.

公开(公告)号：US20170178972A1

公开(公告)日：2017-06-22

申请号：US15447126

申请日：2017-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Chien-Ting Lin ,  Yi-Ren Chen ,  Shou-Wei Hsieh ,  Hsin-Yu Chen ,  Chun-Hao Lin

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/02129 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66803

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

公开(公告)号：US20170133479A1

公开(公告)日：2017-05-11

申请号：US14957623

申请日：2015-12-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ying-Chiao Wang ,  Chao-Hung Lin ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Li-Wei Feng ,  Yu-Hsiang Hung

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/033 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/32

CPC classification number: H01L29/6656 ,  H01L21/0332 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/32 ,  H01L29/66545 ,  H01L29/78

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first spacer around the gate structure, and a contact etch stop layer (CESL) adjacent to the first spacer; forming a cap layer on the gate structure, the first spacer, and the CESL; and removing part of the cap layer for forming a second spacer adjacent to the CESL.

公开(公告)号：US09627268B2

公开(公告)日：2017-04-18

申请号：US14884746

申请日：2015-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Chien-Ting Lin ,  Yi-Ren Chen ,  Shou-Wei Hsieh ,  Hsin-Yu Chen ,  Chun-Hao Lin

IPC: H01L21/8238 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/02129 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

公开(公告)号：US20170103981A1

公开(公告)日：2017-04-13

申请号：US14880284

申请日：2015-10-12

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq ,  Chien-Ting Lin

IPC: H01L27/07 ,  H01L29/06 ,  H01L21/283 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/283 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0629 ,  H01L28/00 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure on a first region and a second fin-shaped structure on a second region; forming a plurality of first gate structures on the first fin-shaped structure, a plurality of second gate structures on the second fin-shaped structure, and an interlayer dielectric (ILD) layer around the first gate structures and the second gate structures; forming a patterned mask on the ILD layer; and using the patterned mask to remove all of the ILD layer from the first region and part of the ILD layer from the second region for forming a plurality of first contact holes in the first region and a plurality of second contact holes in the second region.

公开(公告)号：US09589966B2

公开(公告)日：2017-03-07

申请号：US14724775

申请日：2015-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Chao-Hung Lin ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L27/11 ,  H01L27/02

CPC classification number: H01L27/1104 ,  H01L27/0207

Abstract: A static random access memory (SRAM) is disclosed. The SRAM includes a plurality of SRAM cells on a substrate, in which each of the SRAM cells comprises: a gate structure on the substrate; a first interlayer dielectric (ILD) layer around the gate structure; a first contact plug in the first ILD layer; a second ILD layer on the first ILD layer; and a second contact plug in the second ILD layer and electrically connected to the first contact plug.

Abstract translation: 公开了一种静态随机存取存储器（SRAM）。 SRAM包括在衬底上的多个SRAM单元，其中每个SRAM单元包括：衬底上的栅极结构; 围绕栅极结构的第一层间电介质（ILD）层; 第一ILD层中的第一接触插塞; 第一ILD层上的第二ILD层; 以及在所述第二ILD层中的第二接触插塞，并且电连接到所述第一接触插塞。

公开(公告)号：US20170033015A1

公开(公告)日：2017-02-02

申请号：US15293292

申请日：2016-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Hon-Huei Liu ,  Chao-Hung Lin ,  Nan-Yuan Huang ,  Jyh-Shyang Jenq

IPC: H01L21/8234 ,  H01L29/423 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/7842 ,  H01L29/785

Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, having a first fin structure and a second fin structure disposed thereon, next, a first isolation region is formed between the first fin structure and the second fin structure, a second isolation region is formed opposite the first fin structure from the first isolation region, and at least an epitaxial layer is formed on the side of the first fin structure and the second fin structure, wherein the epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region, in addition, the epitaxial layer has a stepped-shaped sidewall profile.

Abstract translation: 本发明提供一种半导体结构的形成方法，其特征在于，首先，设置具有第一鳍结构和设置在其上的第二鳍结构的衬底，接着，在所述第一鳍结构和所述第二鳍结构之间形成第一隔离区 鳍结构，与第一隔离区相对地形成第二隔离区，并且在第一鳍结构和第二鳍结构的一侧形成至少外延层，其中外延层具有底表面 所述底表面从所述第一鳍结构延伸到所述第二鳍结构，并且所述底表面低于所述第一隔离区域的底表面和所述第二隔离区域的顶表面，此外，所述外延层具有阶梯状 形侧壁轮廓。