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    Semiconductor device including a plurality of semiconductor substrates and method of manufacturing the same
    71.
    发明申请
    Semiconductor device including a plurality of semiconductor substrates and method of manufacturing the same 有权
    包括多个半导体衬底的半导体器件及其制造方法

    公开(公告)号：US20100065858A1

    公开(公告)日：2010-03-18

    申请号：US12461971

    申请日：2009-08-31

    Applicant: Kazuhiko Sugiura

    Inventor： Kazuhiko Sugiura

    IPC: H01L31/02 ,  H01L29/84 ,  H01L21/98

    CPC classification number: G01P15/0802 ,  B81B2201/025 ,  B81C1/00238 ,  B81C2201/019 ,  G01P15/125 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In a semiconductor device, a first semiconductor substrate includes a first element on a first-surface side thereof, and a second semiconductor substrate includes a second element and a wiring part on a first-surface side thereof. The first semiconductor substrate and the second semiconductor substrate are attached with each other in such a manner that a first surface of the first semiconductor substrate is opposite a first surface of the second semiconductor substrate. A hole is provided from a second surface of the first semiconductor substrate to the wiring part through the first semiconductor substrate, and a sidewall of the hole is insulated. A drawing wiring part made of a conductive member fills the hole.

    Abstract translation: 在半导体器件中，第一半导体衬底在其第一表面侧上包括第一元件，第二半导体衬底在其第一表面侧上包括第二元件和布线部。 第一半导体衬底和第二半导体衬底彼此附接，使得第一半导体衬底的第一表面与第二半导体衬底的第一表面相对。 通过第一半导体衬底从第一半导体衬底的第二表面到布线部分设置一个孔，并且孔的侧壁被绝缘。 由导电构件制成的绘图布线部分填充孔。

    Bonding method, device produced by this method, and bonding device
    72.
    发明授权
    Bonding method, device produced by this method, and bonding device 有权
    接合方法，通过该方法制造的器件和接合装置

    公开(公告)号：US07645681B2

    公开(公告)日：2010-01-12

    申请号：US10581430

    申请日：2004-12-02

    Applicant: Masuaki Okada

    Inventor： Masuaki Okada

    IPC: H01L21/30

    CPC classification number: C03C27/06 ,  B81C3/001 ,  B81C2201/019 ,  C03C23/0005 ,  C03C27/00 ,  H01L21/67092 ,  H01L21/76251

    Abstract: Conventional heat bonding and anodic bonding require heating at high temperature and for a long time, leading to poor production efficiency and occurrence of a warp due to a difference in thermal expansion, resulting in a defective device. Such a problem is solved. An upper wafer 7 made of glass and a lower wafer 8 made of Si are surface-activated using an energy wave before performing anodic bonding, thereby performing bonding at low temperature and increasing a bonding strength. In addition, preliminary bonding due to surface activation is performed before main bonding due to anodic bonding is performed in a separate step or device, thereby increasing production efficiency, and enabling bonding of a three-layer structure without occurrence of a warp.

    Abstract translation: 传统的热粘合和阳极接合需要在高温下长时间加热，导致生产效率差和由于热膨胀差导致翘曲的发生，从而导致装置不良。 这个问题解决了。 由玻璃制成的上晶片7和由Si制成的下晶片8在进行阳极接合之前使用能量波进行表面激活，从而在低温下进行接合并提高接合强度。 此外，由于阳极接合在主要接合之前在单独的步骤或装置中执行由于表面活化的预接合，从而提高了生产效率，并且能够在不发生翘曲的情况下进行三层结构的接合。

    Microstructured component and method for its manufacture
    77.
    发明授权
    Microstructured component and method for its manufacture 失效
    微结构元件及其制造方法

    公开(公告)号：US07531229B2

    公开(公告)日：2009-05-12

    申请号：US10618795

    申请日：2003-07-14

    Applicant: Udo-Martin Gomez ,  Franz Laermer

    Inventor： Udo-Martin Gomez ,  Franz Laermer

    IPC: B32B3/02 ,  B60T8/60 ,  B60T8/74 ,  H01L23/15 ,  G01P15/00

    CPC classification number: B81B7/0077 ,  B81B2207/095 ,  B81C1/00301 ,  B81C2201/019 ,  B81C2203/0109 ,  B81C2203/031 ,  G01P15/0802 ,  G01P15/125 ,  Y10T428/239 ,  Y10T428/24917

    Abstract: A microstructured component having a layered construction may allow implementation of component structures having a layer thickness of more than 50 μm, e.g., more than 100 μm. Capping of the component structure may allow vacuum enclosure of the component structure with a hermetically sealed electrical connection. The layered construction of the microstructured component includes a carrier including at least one glass layer, e.g., a PYREX™ layer, a component structure, arranged in a silicon layer, which is bonded to the glass layer, and a cap, which is positioned over the component structure and is also bonded to the glass layer.

    Abstract translation: 具有分层结构的微结构部件可以允许实现层厚度大于50μm，例如大于100μm的组分结构。 组件结构的封盖可以允许具有气密密封的电连接的部件结构的真空外壳。 微结构化部件的分层结构包括载体，其包括至少一个玻璃层，例如PYREX TM层，布置在硅层中的部件结构，其结合到玻璃层，以及帽，其是 位于组件结构上方并且也结合到玻璃层。

    VACUUM PACKAGED SINGLE CRYSTAL SILICON DEVICE
    80.
    发明申请
    VACUUM PACKAGED SINGLE CRYSTAL SILICON DEVICE 失效

    公开(公告)号：US20080261344A1

    公开(公告)日：2008-10-23

    申请号：US12164850

    申请日：2008-06-30

    Applicant: Ijaz H. Jafri ,  Galen P. Magendanz

    Inventor： Ijaz H. Jafri ,  Galen P. Magendanz

    IPC: H01L21/02

    CPC classification number: B81C1/00333 ,  B81B2201/0271 ,  B81C1/00142 ,  B81C2201/019 ,  B81C2203/036 ,  B81C2203/051 ,  H03H3/0072 ,  H03H9/1057 ,  H03H9/2405 ,  H03H9/2447 ,  H03H9/462 ,  H03H2009/02511

    Abstract: A method for forming a vibrating micromechanical structure having a single crystal silicon (SCS) micromechanical resonator formed using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of the base wafer; the active layer of the resonator wafer is bonded directly to the active layer of the base wafer; the handle and dielectric layers of the resonator wafer are removed; windows are opened in the active layer of the resonator wafer; masking the active layer of the resonator wafer with photoresist; a SCS resonator is machined in the active layer of the resonator wafer using silicon dry etch micromachining technology; and the photoresist is subsequently dry stripped. A patterned SCS cover is bonded to the resonator wafer resulting in hermetically sealed chip scale wafer level vacuum packaged devices.

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