公开(公告)号：US09064579B2

公开(公告)日：2015-06-23

申请号：US13722361

申请日：2012-12-20

Applicant: Gen Ohshima

Inventor： Gen Ohshima

IPC: G06F11/00 ,  G11C16/06 ,  G06F13/16 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/16 ,  G06F13/16 ,  G06F2212/1036 ,  G06F2212/1041 ,  G11C16/06 ,  G11C16/102 ,  G11C16/32 ,  G11C16/349

Abstract: According to one embodiment, a semiconductor memory apparatus includes a memory and a speed control unit. The speed control unit calculates a time-varying behavior of a permissible value of an accumulated amount of data written in the non-volatile semiconductor memory, where, after a start of a guaranteed period, data is written in the memory at a constant write speed so that the permissible value at an end time of the guaranteed period is equal to a sum of a first capacity and a second capacity. The first capacity is an accumulated amount of data written in the memory. The second capacity is an accumulated amount of data which is writable in the memory in a remaining time of the guaranteed period based on remaining rewritable times of existing blocks. The speed control unit controls a transmission speed of data from a host based on the permissible value.

Abstract translation: 根据一个实施例，半导体存储装置包括存储器和速度控制单元。 速度控制单元计算写入非易失性半导体存储器的累积数据量的允许值的时变特性，其中在保证期间开始之后以恒定写入速度将数据写入存储器 使得在保证期间的结束时间的允许值等于第一容量和第二容量之和。 第一容量是写入存储器中的累积数据量。 第二容量是基于现有块的剩余可重写时间在保证期间的剩余时间内在存储器中可写入的数据的累积量。 速度控制单元基于允许值来控制来自主机的数据的传输速度。

公开(公告)号：US09053036B2

公开(公告)日：2015-06-09

申请号：US13684838

申请日：2012-11-26

Applicant: LSI Corporation

Inventor： Ashish Jain ,  Kiran B. Dalvi ,  Amit K. Sharma

IPC: G06F12/08 ,  G06F11/00 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F12/0888 ,  G06F11/002 ,  G06F12/0246 ,  G06F12/0866 ,  G06F13/1673 ,  G06F2212/1036 ,  G06F2212/222

Abstract: Aspects of the disclosure pertain to a system and method for providing a flash memory cache input/output throttling mechanism based upon temperature parameters for promoting improved flash life. The mechanism restricts flash memory cache caching of inputs/outputs associated with Least Recently Used data and Most Recently Used data when a temperature of the flash memory is at or above a threshold temperature.

Abstract translation: 本公开的方面涉及用于提供基于温度参数的闪速存储器高速缓存输入/输出节流机构以提高闪光寿命的系统和方法。 当闪存的温度处于或高于阈值温度时，该机制限制与最近最少使用的数据和最近使用的数据相关联的输入/输出的闪速存储器高速缓存。

公开(公告)号：US09021185B2

公开(公告)日：2015-04-28

申请号：US13502739

申请日：2010-11-23

Applicant: Amir Ban

Inventor： Amir Ban

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/02 ,  G11C16/34

CPC classification number: G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/7202 ,  G06F2212/7205 ,  G06F2212/7207 ,  G11C16/349

Abstract: A memory controller and methods for managing efficient writing to a flash memory are presented. Fresh data is written to at least one block of the flash memory. During a space reclamation process, other data, previously written to the flash memory, is relocated to at least one other block of the flash memory, such that the fresh data and the relocated data always are maintained in separate blocks of the flash memory. During writing, an update frequency level is selected for the fresh data from among multiple update frequency levels and the fresh data is written to a block that is associated with the selected update frequency level. During space reclamation, a plurality of blocks, space of which is to be reclaimed, is selected and the valid pages thereof are copied to at least one destination block.

Abstract translation: 提出了一种用于管理对闪速存储器的有效写入的存储器控​​制器和方法。 新鲜数据被写入闪存的至少一个块。 在空间回收处理期间，先前写入闪速存储器的其他数据被重新定位到闪速存储器的至少一个其他块，使得新鲜数据和重新定位的数据总是保持在闪速存储器的单独块中。 在写入期间，对于来自多个更新频率级别的新鲜数据选择更新频率级别，并且将新鲜数据写入与所选择的更新频率级别相关联的块。 在空间回收期间，选择要复原的多个块，其有效页被复制到至少一个目的地块。

公开(公告)号：US20150095546A1

公开(公告)日：2015-04-02

申请号：US14044548

申请日：2013-10-02

Applicant: Alan Bennett ,  Sergey Anatolievich Gorobets

Inventor： Alan Bennett ,  Sergey Anatolievich Gorobets

IPC: G06F3/06

CPC classification number: G06F12/00 ,  G06F3/0649 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2212/1036 ,  G06F2212/7201 ,  G06F2212/7208 ,  G06F2212/7211

Abstract: A method and system are disclosed for remapping logical addresses between memory banks of discrete or embedded multi-bank storage device. The method may include a controller of a storage device tracking a total erase count for a storage device, determining if an erase count imbalance greater than a threshold exists between banks, and then remapping logical address ranges from the highest erase count bank to the lowest erase count bank to even out wear between the banks. The system may include a controller that may maintain a bank routing table, an erase counting mechanism and execute instructions for triggering a remapping process to remap an amount of logical addresses such that an address range is reduced for a hotter bank and increased for a colder bank.

Abstract translation: 公开了用于重新映射离散或嵌入式多存储存储设备的存储体之间的逻辑地址的方法和系统。 该方法可以包括跟踪存储设备的总擦除计数的存储设备的控制器，确定在存储体之间是否存在大于阈值的擦除计数不平衡，然后将逻辑地址范围从最高擦除计数存储区重新映射到最低擦除 计数银行甚至在银行之间穿戴。 系统可以包括可以维护银行路由表，擦除计数机制和执行指令的控制器，用于触发重映射处理以重新映射逻辑地址的数量，使得对于较热的银行减少地址范围并且对于较冷的银行而言增加 。

公开(公告)号：US20150058553A1

公开(公告)日：2015-02-26

申请号：US14295359

申请日：2014-06-04

Applicant: Acer Incorporated

Inventor： Po-Wei Wu ,  Ta-Wei Chang ,  Hsung-Pin Chang

IPC: G06F12/08

CPC classification number: G06F12/0888 ,  G06F12/0873 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/2146 ,  G06F2212/217 ,  G06F2212/222 ,  G06F2212/224 ,  G06F2212/7208

Abstract: A data writing method, a hard disc module, and a data writing system for writing data into the hard disc module are provided, wherein the hard disc module includes a plurality of memory units. The data writing method includes the following steps. A cache data is received and a data class of the cache data is determined. If the data class of the cache data belongs to a first type, the cache data is distributed and written to the memory units. If the data class of the cache data belongs to a second type, the cache data is written to one of the memory units.

Abstract translation: 提供了一种用于将数据写入硬盘模块的数据写入方法，硬盘模块和数据写入系统，其中硬盘模块包括多个存储单元。 数据写入方法包括以下步骤。 接收缓存数据，并确定高速缓存数据的数据类别。 如果高速缓存数据的数据类别属于第一类型，则高速缓存数据被分配并写入存储器单元。 如果高速缓存数据的数据类别属于第二类型，则将高速缓存数据写入其中一个存储单元。

公开(公告)号：US20150058530A1

公开(公告)日：2015-02-26

申请号：US13973162

申请日：2013-08-22

Applicant: Gautham Reddy ,  Nian Niles Yang ,  Alexandra Bauche ,  Nagdi Tafish ,  Michael Zhu

Inventor： Gautham Reddy ,  Nian Niles Yang ,  Alexandra Bauche ,  Nagdi Tafish ,  Michael Zhu

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/0685 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211 ,  G11C16/349 ,  G11C29/82

Abstract: A memory system or flash card may include a dynamic system-level process for the management of blocks in the different memory pools. There may be spare blocks available to the pools that are over provisioned to the pool which increases the efficiency of data compaction and helps reduce the average hot count for that pool and compensate for the grown defects. The block wear and grown defects in each memory pool may be tracked so that remaining spare blocks can be re-allocated.

Abstract translation: 存储器系统或闪存卡可以包括用于管理不同存储器池中的块的动态系统级过程。 池中可能有可用的备用块，这些池可以提供给池，从而提高了数据压缩的效率，并有助于减少该池的平均热计数并补偿增长的缺陷。 可以跟踪每个存储池中的块磨损和生长缺陷，使得可以重新分配剩余的备用块。

公开(公告)号：US20150052417A1

公开(公告)日：2015-02-19

申请号：US14459584

申请日：2014-08-14

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yohei HASEGAWA ,  Shigehiro Asano ,  Tokumasa Hara

IPC: G06F11/10 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F11/1012 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/7207

Abstract: According to an embodiment, a memory system includes multiple nonvolatile memories to/from each of which data can be written/read independently of one another; and a controller configured to control writing of data to and reading of data from the nonvolatile memories. Each of the nonvolatile memories includes a data storage including a normal data storage area for storing the data and a redundant data storage area for writing the data avoiding defect positions in the normal data storage area; and a defect information storage configured to store defect information indicating information on a defect of the data storage included in another nonvolatile memory different from the present nonvolatile memory.

Abstract translation: 根据实施例，存储器系统包括多个非易失性存储器，每个数据可独立于彼此写入/读取; 以及控制器，被配置为控制数据写入和从非易失性存储器读取数据。 每个非易失性存储器包括数据存储器，其包括用于存储数据的正常数据存储区域和用于将避免缺陷位置的数据写入正常数据存储区域的冗余数据存储区域; 以及缺陷信息存储器，被配置为存储指示关于与所述非易失性存储器不同的另一非易失性存储器中包括的数据存储器的缺陷的信息的缺陷信息。

公开(公告)号：US08954655B2

公开(公告)日：2015-02-10

申请号：US13741299

申请日：2013-01-14

Applicant: Western Digital Technologies, Inc.

Inventor： Sebastien A. Jean ,  Robert L. Horn

IPC: G06F12/02 ,  G06F13/40

CPC classification number: G06F12/0246 ,  G06F13/404 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/214 ,  G06F2212/7204 ,  G06F2212/7206 ,  G11C2211/5641

Abstract: Disclosed herein is an architecture that pairs a controller with a NVM (non-volatile memory) storage system. The NVM storage system includes a bridge device that communicates with the controller. In one embodiment, the bridge device allows for certain data locations (blocks, pages or units at any other granularity) in the flash dies to be (1) placed into a reserved mode where data access is prevented (2) assigned into an SLC (Single-Level Cell) mode or an MLC (Multi-Level Cell) mode in response to controller command, (3) made available for data access after the assignment of mode. This flexibility enables the controller to increase SLC mode or MLC mode data locations based on run-time conditions. In one embodiment, the assignment of the reserved data locations is performed in a way to ensure that warranty conditions imposed by the memory vendors are observed.

Abstract translation: 这里公开了一种将控制器与NVM（非易失性存储器）存储系统配对的架构。 NVM存储系统包括与控制器通信的桥接设备。 在一个实施例中，桥接器件允许闪存芯片中的某些数据位置（任何其他粒度的块，页或单元）被（1）置于预防模式，其中防止数据访问（2）被分配到SLC（ 单级单元）模式或MLC（多级单元）模式响应控制器命令，（3）在分配模式后可用于数据访问。 这种灵活性使控制器能够根据运行时间条件增加SLC模式或MLC模式数据位置。 在一个实施例中，保留的数据位置的分配以确保遵守内存供应商施加的保修条件的方式被执行。

公开(公告)号：US20150026386A1

公开(公告)日：2015-01-22

申请号：US13943762

申请日：2013-07-16

Applicant: Yogesh B. Wakchaure ,  David J. Pelster ,  Xin Guo

Inventor： Yogesh B. Wakchaure ,  David J. Pelster ,  Xin Guo

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7204 ,  G06F2212/7205 ,  G06F2212/7207 ,  G06F2212/7208 ,  G06F2212/7209 ,  G06F2212/7211 ,  G11C11/5635 ,  G11C16/10 ,  G11C16/102 ,  G11C16/16 ,  G11C16/32 ,  G11C16/349 ,  G11C16/3495

Abstract: Computer processor hardware receives notification that data stored in a region of storage cells in a non-volatile memory system stores invalid data. In response to the notification, the computer processor hardware marks the region as storing invalid data. The computer processor hardware controls the magnitude of erase dwell time (i.e., the amount of time that one or more cells are set to an erased state) associated with overwriting of the invalid data in the storage cells with replacement data. For example, to re-program respective storage cells, the data manager must erase the storage cells and then program the storage cells with replacement data. The data management logic can control the erase dwell time to be less than a threshold time value to enhance a life of the non-volatile memory system.

Abstract translation: 计算机处理器硬件接收存储在非易失性存储器系统中的存储单元区域中的数据存储无效数据的通知。 响应于该通知，计算机处理器硬件将该区域标记为存储无效数据。 计算机处理器硬件控制与用替换数据重写存储单元中的无效数据相关联的擦除驻留时间的大小（即，一个或多个单元被设置为擦除状态的时间量）。 例如，为了重新编程各个存储单元，数据管理器必须擦除存储单元，然后用替换数据对存储单元进行编程。 数据管理逻辑可以将擦除停留时间控制为小于阈值时间值以增强非易失性存储器系统的寿命。

公开(公告)号：US08918581B2

公开(公告)日：2014-12-23

申请号：US13437006

申请日：2012-04-02

Applicant: KY Srinivasan

Inventor： KY Srinivasan

IPC: G06F12/02 ,  G06F12/08

CPC classification number: G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0871 ,  G06F2212/1024 ,  G06F2212/1036 ,  G06F2212/466

Abstract: A storage management system decouples application write requests from write requests to a flash-based storage device. By placing a layer of software intelligence between application requests to write data and the storage device, the system can make more effective decisions about when and where to write data that reduce wear and increase performance of the storage device. An application has a set of performance characteristics and writes data with a frequency that is appropriate for the application, but not necessarily efficient for the hardware. By analyzing how data is being used by an application, the system can strategically place data in the storage device or even avoid using the storage device altogether for some operations to minimize wear. One technique for doing this is to create an in-memory cache that acts as a buffer between the application requests and the storage hardware.

Abstract translation: 存储管理系统将应用写入请求从写入请求分离到基于闪存的存储设备。 通过在写入数据的应用程序请求和存储设备之间放置一层软件智能，系统可以更有效地决定写入数据的时间和地点，从而降低损耗并提高存储设备的性能。 应用程序具有一组性能特征，并且写入具有适用于应用程序的频率的数据，但不一定对硬件有效。 通过分析应用程序如何使用数据，系统可以将数据策略性地放置在存储设备中，甚至避免使用存储设备进行某些操作，以最大限度地减少磨损。 一种这样做的技术是创建一个内存缓存，作为应用程序请求和存储硬件之间的缓冲区。