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    Integrated counter in memory device
    71.
    发明授权
    Integrated counter in memory device 有权

    公开(公告)号：US11862291B2

    公开(公告)日：2024-01-02

    申请号：US17783118

    申请日：2020-12-03

    Applicant: METACNI CO., LTD.

    Inventor： Young Seung Kim ,  Mi Hwa Lim ,  Dong Min Lim

    IPC: G11C7/22 ,  G11C5/05 ,  G11C7/10

    CPC classification number: G11C7/222 ,  G11C5/05 ,  G11C7/1009 ,  G11C7/1018 ,  G11C7/1036

    Abstract: A memory device according to the present invention comprises: a memory cell array in which memory cells are connected to wordlines and bitlines in a matrix form; and a control circuit for programming the memory cells or controlling a read operation, according to a start address, a burst length, a latency length, and a program or read command which are transmitted from a host, wherein the control circuit may comprise: a pulse generation unit for generating register pulses and counter pulses in synchronization with an operation clock; and a counter that sets the start address in synchronization with the register pulses, counts the number of counter pulses corresponding to the sum of the latency length and the burst length, and increases an address from the start address to the sum of the start address and the burst length.

    Techniques for performing command address in interface training on a dynamic random-access memory
    73.
    发明授权
    Techniques for performing command address in interface training on a dynamic random-access memory 有权

    公开(公告)号：US11742006B2

    公开(公告)日：2023-08-29

    申请号：US17523778

    申请日：2021-11-10

    Applicant: NVIDIA CORPORATION

    Inventor： Robert Bloemer ,  Gautam Bhatia

    IPC: G11C7/10 ,  H03K19/21

    CPC classification number: G11C7/109 ,  G11C7/1036 ,  G11C7/1063 ,  H03K19/21

    Abstract: Various embodiments include a memory device that is capable of performing command address interface training operations, to determine that certain timing conditions are met, with fewer I/O pins relative to prior approaches. Prior approaches for command address interface training involve loading data via a set of input pins, a clock signal, and a clock enable signal that identifies when the input pins should be sampled. Instead, the disclosed memory device generates a data pattern within the memory device that matches the data pattern continuously being transmitted to the memory device by an external memory controller. The memory device compares the generated data pattern with the received data pattern and transmits the result of the comparison on one or more data output pins. The memory controller receives and analyzes the result of the comparison to determine whether the command address interface training passed or failed.

    METHODS AND DEVICES FOR FLEXIBLE RAM LOADING
    75.
    发明公开
    METHODS AND DEVICES FOR FLEXIBLE RAM LOADING 审中-公开

    公开(公告)号：US20230230650A1

    公开(公告)日：2023-07-20

    申请号：US17580458

    申请日：2022-01-20

    Applicant: STMicroelectronics S.r.l.

    Inventor： Gabriele Solcia

    IPC: G11C29/36 ,  G11C29/46 ,  G11C29/12 ,  G11C7/10 ,  H03K19/173 ,  H03K19/20

    CPC classification number: G11C29/36 ,  G11C7/1036 ,  G11C29/46 ,  G11C29/1201 ,  H03K19/20 ,  H03K19/1737 ,  G11C2029/3602

    Abstract: A flexible RAM loader including a shift register that includes a first data section coupled with a serial data input, and a second data section selectively coupled with a first parallel data input. The shift register is configured to load data serially from the serial data input to the first data section and the second data section when the second data section is uncoupled from the first parallel data input, and, when the second data section is coupled with the first parallel data input, configured to load data in parallel from the serial data input into the first data section and from the first parallel data input into the second data section. The flexible RAM loader also including a test register comprising a selection bit to couple the second data section with the first parallel data input.

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