公开(公告)号：US20150102494A1

公开(公告)日：2015-04-16

申请号：US14219042

申请日：2014-03-19

Applicant: Wistron Corporation

Inventor： Hui-Ying Chou ,  Lee-Chieh Kang

IPC: H01L23/00 ,  H01L23/13

CPC classification number: H01L24/81 ,  H01L23/13 ,  H01L23/528 ,  H01L23/53204 ,  H05K3/0005 ,  H05K3/3442 ,  H05K3/4007 ,  H05K2201/0969 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A method for forming voids corresponding to pads of SMT components is provided. The method comprises following steps: One or more condition parameters are inputted into a searching unit. The searching unit searches all of the pads with reference to the condition parameters to obtain a pre-selected group of pads. A judgment unit is provided to determine whether each pad of the pre-selected group of pads meets a pre-determined processing requirement to generate a to-be-processed group of pads. An execution unit executes a void formation step with reference to corner coordinates of each of the to-be-processed group of pads, so as to form at least a void at the portion of a contact surface corresponding to a corner of the pad. In an embodiment, four voids which are related to respective corners of each pad of the to-be-processed group are formed at the contact surface accordingly.

Abstract translation: 提供了一种形成对应于SMT部件的焊盘的空隙的方法。 该方法包括以下步骤：将一个或多个条件参数输入到搜索单元。 参考条件参数，搜索单元搜索所有的焊盘，以获得预选的焊盘组。 提供判断单元以确定预先选择的焊盘组中的每个焊盘是否满足预定的处理要求以生成要处理的焊盘组。 执行单元参照要处理的一组焊盘的角坐标来执行空隙形成步骤，以便在与焊盘的角部相对应的接触表面的部分处形成至少一个空隙。 在一个实施例中，相应地在接触表面处形成与被处理组的每个焊盘的各个角相关的四个空隙。

公开(公告)号：US20140306346A1

公开(公告)日：2014-10-16

申请号：US14310612

申请日：2014-06-20

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Kenichi Watanabe

IPC: H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

公开(公告)号：US08722531B1

公开(公告)日：2014-05-13

申请号：US13666792

申请日：2012-11-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Hung Lin ,  Chi-Yu Chou ,  Kuei-Pin Lee ,  Chen-Kuang Lien ,  Yu-Chang Hsiao ,  Yao-Hsiang Liang ,  Yu-Min Chang

IPC: H01L21/4763

CPC classification number: H01L21/76846 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76867 ,  H01L21/76877 ,  H01L23/53204 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming an interconnect structure includes forming a dielectric layer overlying a substrate, forming a metal-containing layer in the dielectric layer, forming a barrier layer overlying the metal-containing layer, and performing a thermal process to form a metal oxide layer underlying the conductive layer. The metal oxide layer is a barrier layer formed at the boundary between the dielectric layer and the metal-containing layer.

Abstract translation: 形成互连结构的方法包括形成覆盖在基板上的电介质层，在电介质层中形成含金属层，形成覆盖在含金属层上的阻挡层，以及进行热处理以形成基底的金属氧化物层 导电层。 金属氧化物层是在电介质层和含金属层之间的边界处形成的阻挡层。

公开(公告)号：US20140061928A1

公开(公告)日：2014-03-06

申请号：US13677861

申请日：2012-11-15

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chang-Fu Lin ,  Ho-Yi Tsai ,  Chin-Tsai Yao ,  Jui-Chung Ho ,  Ching-Hui Hung

IPC: H01L23/532

CPC classification number: H01L23/53204 ,  H01L24/00 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/05584 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/16503 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: An interconnection structure for being formed on bonding pads of a substrate in a semiconductor package is provided. The interconnection structure includes a nickel layer formed on each of the bonding pads, a metal layer formed on the nickel layer, and a solder material formed on the metal layer. The metal layer is made of one of gold, silver, lead and copper, and has a thickness in the range of 0.5 to 5 um. As such, when the solder material is reflowed to form solder bumps, no nickel-tin compound is formed between the solder bumps and the metal layer, thereby avoiding cracking or delamination of the solder bumps.

Abstract translation: 提供了用于形成在半导体封装中的衬底的焊盘上的互连结构。 互连结构包括形成在每个接合焊盘上的镍层，形成在镍层上的金属层和形成在金属层上的焊料材料。 金属层由金，银，铅和铜之一制成，厚度为0.5〜5μm。 因此，当焊料材料回流以形成焊料凸块时，在焊料凸块和金属层之间不形成镍锡化合物，从而避免焊料凸块的开裂或分层。

公开(公告)号：US08633594B2

公开(公告)日：2014-01-21

申请号：US13548792

申请日：2012-07-13

Applicant: Kenichi Watanabe

Inventor： Kenichi Watanabe

IPC: H01L29/74 ,  H01L27/108

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

公开(公告)号：US20130200481A1

公开(公告)日：2013-08-08

申请号：US13834418

申请日：2013-03-15

Applicant: FUJITSU SEMICONDUCTOR LIMITED

Inventor： Kenichi Watanabe

IPC: H01L29/06

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

公开(公告)号：US07301241B2

公开(公告)日：2007-11-27

申请号：US10622614

申请日：2003-07-21

Applicant: Kenichi Watanabe

Inventor： Kenichi Watanabe

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/52 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a . A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract translation: 半导体器件具有形成在衬底10上的绝缘膜40,42; 埋置在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及掩埋在孔形通孔60和槽形通孔66a中的埋入导体70,72a。 形成沟槽状的通孔66a的宽度小于孔状的通路孔66的宽度。 可以防止掩埋导体的不充分填充和层间绝缘膜的开裂。 导体插头上的步骤可以减少。 因此，可以防止与上部互连层的不良接触以及在形成膜中发生的问题。

公开(公告)号：US20040021227A1

公开(公告)日：2004-02-05

申请号：US10622614

申请日：2003-07-21

Applicant: Fujitsu Limited

Inventor： Kenichi Watanabe

IPC: H01L023/48 ,  H01L021/4763

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

Abstract translation: 半导体器件包括：形成在衬底10上的绝缘膜40,42; 埋置在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽状通路孔66a中的埋入导体70,72a，其中，形成沟槽形通孔66a的宽度小于孔的宽度 由此，能够防止埋入导体的填充不良，能够防止层间绝缘膜的破裂。 可以减少导体插塞上的步骤，使得该步骤不会影响上互连层和绝缘层。 因此，可以防止与上部互连层的不良接触以及在形成膜中发生的问题，从而可以使半导体器件具有高的耐水性和高的互连可靠性。

公开(公告)号：US20030122175A1

公开(公告)日：2003-07-03

申请号：US10034596

申请日：2001-12-28

Inventor： Peter Van Buskirk

IPC: H01L027/108 ,  H01L029/76 ,  H01L029/94 ,  H01L031/119

CPC classification number: H01L27/0805 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/53204 ,  H01L27/222 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A passive transmission line element (device) monolithically integrated into an integrated circuit at one or more levels of the integrated circuit by using a damascene process to delineate a conductive line such that at least the bottom surface and sidewalls of the conductive line are embedded in an enhancement layer having high permeability and/or high permitivity. Optionally a second enhancement layer may cover the conductive line, to completely embed or surround the conductive line with permeability and/or permitivity enhancement material. The passive transmission line device comprising the conductive line and the enhancement layer thus has enhanced distributed inductance and/or enhanced distributed capacitance. In addition, the passive transmission line device may optionally have enhanced distributed resistance as well by forming the conductive line from resistive (i.e., not highly conductive) material.

Abstract translation: 一种无源传输线元件（器件），其通过使用镶嵌工艺来划分导电线，在集成电路的一个或多个层次上单片集成到集成电路中，使得至少导电线的底表面和侧壁嵌入 增强层具有高渗透性和/或高的介电常数。 可选地，第二增强层可以覆盖导电线，以完全嵌入或围绕导电线与导电性和/或吸收增强材料。 因此，包括导线和增强层的无源传输线装置具有增强的分布电感和/或增强的分布电容。 此外，无源传输线装置也可以通过从电阻（即不是高导电性）材料形成导线而可选地具有增强的分布电阻。

公开(公告)号：US5945737A

公开(公告)日：1999-08-31

申请号：US968895

申请日：1997-11-06

Applicant: Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Fran.cedilla.ois Max d'Heurle ,  Qi-Zhong Hong

Inventor： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Fran.cedilla.ois Max d'Heurle ,  Qi-Zhong Hong

IPC: G02B1/10 ,  C04B41/87 ,  C23C8/02 ,  C23C8/06 ,  C23C26/00 ,  C30B25/06 ,  C30B29/06 ,  C30B29/08 ,  C30B29/42 ,  C30B33/02 ,  G11B5/255 ,  G11B5/31 ,  G11B5/60 ,  G11B5/78 ,  G11B7/12 ,  H01L21/20 ,  H01L21/203 ,  H01L21/285 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L29/43

CPC classification number: H01L24/10 ,  C23C26/00 ,  C23C8/02 ,  G11B5/255 ,  G11B5/3106 ,  G11B5/3109 ,  G11B5/78 ,  G11B7/122 ,  H01L21/321 ,  H01L21/76838 ,  H01L23/53204 ,  H01L24/13 ,  G11B5/313 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01105 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14

Abstract: A device having a thin film and/or a solder ball formed on a substrate. The thin film and the solder ball each include a metal and a compound that includes an oxide, nitride, or carbide precipitate of an expandable element or a contractible element. The compound is distributed in the metal to control the tensile and compressive stresses and mechanical properties of the thin film and the solder ball.

Abstract translation: 具有形成在基板上的薄膜和/或焊球的装置。 薄膜和焊球各自包括金属和包含可膨胀元件或可收缩元件的氧化物，氮化物或碳化物沉淀物的化合物。 化合物分布在金属中以控制薄膜和焊球的拉伸和压缩应力和机械性能。