公开(公告)号：US20030186472A1

公开(公告)日：2003-10-02

申请号：US10428937

申请日：2003-05-05

Applicant: FUJITSU LIMITED.

Inventor： Kenichi Watanabe

IPC: H01L021/66 ,  H01L021/4763

CPC classification number: H01L21/76816 ,  H01L21/76802 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A substrate defining an insulating surface layer portion and formed with a wiring groove filled with a wiring line the wiring line is electrically connected to a conductive member. The conductive member occupies an area larger than an area of the wiring line as viewed along a line parallel to a normal to the first surface. An insulating first film is formed on the first surface. A via hole is formed through the first film. The via hole is formed so that a boundary between the wiring line and the insulating surface layer portion passes through the inside of the via hole. The bottom of the via hole is observed with an apparatus for obtaining image information by utilizing secondary electrons and reflection electrons, to judge whether a state of the bottom of the via hole is accepted or rejected.

Abstract translation: 限定绝缘表面层部分并且形成有填充有布线的布线槽的衬底的衬底电连接到导电构件。 导电构件沿着与第一表面的法线平行的线观察，占据比布线的面积大的面积。 在第一表面上形成绝缘的第一膜。 通过第一膜形成通孔。 通孔形成为使得布线和绝缘表面层部分之间的边界通过通孔的内部。 通过利用二次电子和反射电子获得图像信息的装置来观察通孔的底部，以判断通孔底部的状态是否被接受或拒绝。

公开(公告)号：US20030116852A1

公开(公告)日：2003-06-26

申请号：US10309113

申请日：2002-12-04

Applicant: Fujitsu Limited

Inventor： Kenichi Watanabe ,  Noriyoshi Shimizu ,  Takashi Suzuki

IPC: H01L021/50 ,  H01L023/48

CPC classification number: H01L21/76811 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76838 ,  H01L21/7684 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is provided a semiconductor device which comprises a second insulating film formed on a substantially flat surface, on which a surface of a first wiring and a surface of a first insulating film are continued, to cover the first wiring, a wiring trench formed in the second insulating film, connection holes formed in the second insulating film to extend from the wiring trench to the first wiring, dummy connection holes formed in the second insulating film to extend from the wiring trench to a non-forming region of the first wiring, and a second wiring buried in the connection holes and the wiring trench to be connected electrically to the first wiring and also buried in the dummy connection holes, and formed such that a surface of the second wiring and a surface of the second insulating film constitute a substantially flat surface.

Abstract translation: 提供了一种半导体器件，其包括形成在基本平坦的表面上的第二绝缘膜，第一布线的表面和第一绝缘膜的表面在其上连续地覆盖第一布线，形成在第一布线中的布线沟槽 第二绝缘膜，形成在第二绝缘膜中的从布线沟槽延伸到第一布线的连接孔，形成在第二绝缘膜中的虚拟连接孔，以从布线沟槽延伸到第一布线的非形成区域;以及 埋入连接孔中的第二布线和要与第一布线电连接并且还埋入虚拟连接孔中的布线沟槽，并且形成为使得第二布线的表面和第二绝缘膜的表面基本上构成 平坦的表面。

公开(公告)号：US20030073257A1

公开(公告)日：2003-04-17

申请号：US10073922

申请日：2002-02-14

Applicant: FUJITSU LIMITED

Inventor： Kenichi Watanabe

IPC: H01L021/66 ,  G01R031/26 ,  H01L021/4763

CPC classification number: H01L21/76816 ,  H01L21/76802 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A substrate defining an insulating surface layer portion and formed with a wiring groove filled with a wiring line the wiring line is electrically connected to a conductive member. The conductive member occupies an area larger than an area of the wiring line as viewed along a line parallel to a normal to the first surface. An insulating first film is formed on the first surface. A via hole is formed through the first film. The via hole is formed so that a boundary between the wiring line and the insulating surface layer portion passes through the inside of the via hole. The bottom of the via hole is observed with an apparatus for obtaining image information by utilizing secondary electrons and reflection electrons, to judge whether a state of the bottom of the via hole is accepted or rejected.

Abstract translation: 限定绝缘表面层部分并且形成有填充有布线的布线槽的衬底的衬底电连接到导电构件。 导电构件沿着与第一表面的法线平行的线观察，占据比布线的面积大的面积。 在第一表面上形成绝缘的第一膜。 通过第一膜形成通孔。 通孔形成为使得布线和绝缘表面层部分之间的边界通过通孔的内部。 通过利用二次电子和反射电子获得图像信息的装置来观察通孔的底部，以判断通孔底部的状态是否被接受或拒绝。

公开(公告)号：US20020151190A1

公开(公告)日：2002-10-17

申请号：US10105190

申请日：2002-03-26

Applicant: FUJITSU LIMITED

Inventor： Hiroshi Kudo ,  Masanobu Ikeda ,  Kenichi Watanabe ,  Yoshiyuki Ohkura

IPC: H01L021/31 ,  H01L021/469 ,  H01L023/58

CPC classification number: H01L23/5329 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76837 ,  H01L21/7684 ,  H01L21/76882 ,  H01L23/5222 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A semiconductor device includes a multilayer interconnection structure including an organic interlayer insulation film in which a conductor pattern is formed by a damascene process, wherein the organic interlayer insulation film carries thereon an organic spin-on-glass film.

Abstract translation: 半导体器件包括多层互连结构，其包括通过镶嵌工艺形成导体图案的有机层间绝缘膜，其中有机层间绝缘膜承载有机旋涂玻璃膜。

公开(公告)号：US20020008323A1

公开(公告)日：2002-01-24

申请号：US09735479

申请日：2000-12-14

Applicant: Fujitsu Limited, Kawasaki, Japan

Inventor： Kenichi Watanabe ,  Daisuke Komada ,  Fumihiko Shimpuku

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L21/76808 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76813 ,  H01L21/76829 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having: an underlie having a conductive region in the surface layer of the underlie; an insulating etch stopper film covering the surface of the underlie; an interlayer insulating film formed on the insulating etch stopper film; a wiring trench formed in the interlayer insulating film, the wiring trench having a first depth from the surface of the interlayer insulating film; a contact hole extending from the bottom surface of the wiring trench to the surface of the conductive region; and a dual damascene wiring layer embedded in the wiring trench and the contact hole, wherein the interlayer insulating film includes a first kind of an insulating layer surrounding the side wall and bottom surface of the wiring trench and a second kind of an insulating layer having etching characteristics different from the first kind of the insulating layer. The semiconductor device is provided which can protect the underlying conductive region sufficiently and has a dual damascene wiring layer having a high reliability and a small wiring capacitance.

Abstract translation: 一种半导体器件，具有：在基底的表层中具有导电区域的基底; 覆盖基底表面的绝缘蚀刻阻挡膜; 形成在所述绝缘蚀刻停止膜上的层间绝缘膜; 形成在所述层间绝缘膜中的布线沟槽，所述布线沟槽具有从所述层间绝缘膜的表面的第一深度; 从所述布线沟槽的底表面延伸到所述导电区域的表面的接触孔; 以及嵌入在所述布线沟槽和所述接触孔中的双镶嵌布线层，其中所述层间绝缘膜包括围绕所述布线沟槽的侧壁和底面的第一种绝缘层和具有蚀刻的第二种绝缘层 特性不同于第一种绝缘层。 提供了可以充分保护下面的导电区域并具有高可靠性和小布线电容的双镶嵌布线层的半导体器件。

公开(公告)号：US20030173675A1

公开(公告)日：2003-09-18

申请号：US10349934

申请日：2003-01-24

Applicant: FUJITSU LIMITED

Inventor： Kenichi Watanabe ,  Michiari Kawano ,  Hiroshi Namba ,  Kazuo Sukegawa ,  Takumi Hasegawa ,  Toyoji Sawada ,  Junichi Mitani

IPC: H01L023/52 ,  H01L023/04 ,  H01L023/053 ,  H01L023/48 ,  H01L029/40

CPC classification number: G03F1/26 ,  G03F1/32 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in nullLnull shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.

公开(公告)号：US20030001267A1

公开(公告)日：2003-01-02

申请号：US09987012

申请日：2001-11-13

Applicant: FUJITSU LIMITED

Inventor： Kenichi Watanabe

IPC: H01L023/48

CPC classification number: H01L21/76807 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76828 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/12044 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor wafer device, includes the steps of: (a) forming lower wiring patterns over a semiconductor wafer, the lower wiring patterns being connected to semiconductor elements in a circuit area; (b) forming an interlevel insulating film with a planarized surface over the semiconductor wafer, covering the lower wiring patterns and having a planarized surface; and (c) forming via conductors connected to the lower wiring patterns and wiring patterns disposed on the via conductors in the circuit area and conductor patterns corresponding to the wiring patterns in a peripheral area other than the circuit area, by embedding the via conductors, wiring patterns and conductor patterns in the interlevel insulating film, the conductive patterns being electrically isolated. The method can form a desired wiring structure and can prevent an increase of the percentage of defective devices in an effective wafer area.

Abstract translation: 一种制造半导体晶片装置的方法包括以下步骤：（a）在半导体晶片上形成较低的布线图案，所述下布线图案与电路区域中的半导体元件连接; （b）在半导体晶片上形成具有平坦化表面的层间绝缘膜，覆盖下布线图案并具有平坦化表面; 和（c）通过嵌入通孔导体，布线连接到电路区域中连接到下布线图案和配置在通路导体上的布线图案的通孔导体和对应于电路区域以外的周边区域中的布线图案的导体图案 图案和导体图案，导电图案是电隔离的。 该方法可以形成期望的布线结构，并且可以防止有效晶片区域中的有缺陷的器件的百分比的增加。

公开(公告)号：US20030015802A1

公开(公告)日：2003-01-23

申请号：US10242623

申请日：2002-09-13

Applicant: FUJITSU LIMITED

Inventor： Kenichi Watanabe

IPC: H01L021/44 ,  H01L023/48 ,  H01L029/40

CPC classification number: H01L21/76808 ,  H01L21/76838 ,  H01L23/5258 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A semiconductor device includes a first insulating layer which is formed above a semiconductor substrate including a plurality of semiconductor elements and which includes lower-layer damascene wiring, a second insulating layer which is formed on the first insulating layer and which includes a second damascene wiring and an aligning wiring pattern forming a first step, and a first aligning surface wiring pattern including a surface wiring pattern to cover the second damascene wiring and a first aligning surface wiring pattern which is formed on the aligning wiring pattern and which has a second step reflecting the first step. The surface wiring pattern and the first aligning surface wiring pattern are formed using one surface wiring layer. A novel multilayer wiring structure thus obtained is suitably manufactured by the damascene process.

Abstract translation: 半导体器件包括：第一绝缘层，其形成在包括多个半导体元件的半导体衬底之上，并且包括下层镶嵌布线;第二绝缘层，形成在第一绝缘层上并且包括第二镶嵌布线; 形成第一台阶的对准布线图案和包括表面布线图案以覆盖第二镶嵌布线的第一对准表面布线图案和形成在对准布线图案上的第一对准表面布线图案，并且具有反映 第一步。 表面布线图案和第一对准表面布线图案使用一个表面布线层形成。 这样获得的新型多层布线结构适当地通过镶嵌工艺制造。

公开(公告)号：US20040021227A1

公开(公告)日：2004-02-05

申请号：US10622614

申请日：2003-07-21

Applicant: Fujitsu Limited

Inventor： Kenichi Watanabe

IPC: H01L023/48 ,  H01L021/4763

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

Abstract translation: 半导体器件包括：形成在衬底10上的绝缘膜40,42; 埋置在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽状通路孔66a中的埋入导体70,72a，其中，形成沟槽形通孔66a的宽度小于孔的宽度 由此，能够防止埋入导体的填充不良，能够防止层间绝缘膜的破裂。 可以减少导体插塞上的步骤，使得该步骤不会影响上互连层和绝缘层。 因此，可以防止与上部互连层的不良接触以及在形成膜中发生的问题，从而可以使半导体器件具有高的耐水性和高的互连可靠性。

公开(公告)号：US20030227089A1

公开(公告)日：2003-12-11

申请号：US10454667

申请日：2003-06-05

Applicant: FUJITSU LIMITED

Inventor： Kenichi Watanabe ,  Michiari Kawano

IPC: H01L021/4763

CPC classification number: H01L21/76843 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76838 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/53238 ,  H01L23/564 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: After formation of a contact pattern on a semiconductor substrate, a first wiring pattern composed of a first barrier metal film and a first conductor pattern is formed on the contact pattern. A moisture-proof ring is formed which has such a structure that an outer peripheral portion, covering a sidewall face on the outer peripheral side of the first conductor pattern, of the first barrier metal film, is in contact at the upper end portion with a barrier metal bottom face portion, covering the bottom face of a via contact portion, of a second barrier metal film. This results in formation of a barrier metal film such as Ta, TiN, or the like, with no discontinuation, in the whole region from the semiconductor substrate to an silicon oxide film being the uppermost layer, thereby improving adhesiveness for prevention of cracks and entry of moisture.

Abstract translation: 在半导体衬底上形成接触图形之后，在接触图形上形成由第一阻挡金属膜和第一导体图案构成的第一布线图案。 形成防潮环，其具有使第一阻挡金属膜的覆盖第一导体图案的外周侧的侧壁面的外周部与上端部接触的结构， 阻挡金属底面部分，覆盖第二阻挡金属膜的通孔接触部分的底面。 这导致在从半导体衬底到作为最上层的氧化硅膜的整个区域中形成诸如Ta，TiN等的阻挡金属膜，而不会中断，从而提高用于防止裂纹和入口的粘附性 的水分。